can LPC4330 i2s interface to a slave codec with combined tx and rx bclk?

[lpcware]

Content originally posted in LPCWare by acamilo on Fri Sep 13 22:37:14 MST 2013
Hello, i'm trying to interface a NAU8811 to i2s0 on a LPC4330.

The codec has an i2c interface with 4 connections. A shared bit clock, data in/out and a channel clock(WS).
A MCLK is generated internally based on the BCLK.

Is it possible to use one clock and WS for both tx and rx on the 4330 instead of a seperate TX_SCK,TX_WS and RX_SCK,RX_WS?

Thanks.

[lpcware]

Content originally posted in LPCWare by Pacman on Sun Sep 15 11:24:20 MST 2013
No problem. Great that you got the question answered, please post your results. :)
The best source for information I had so far is the User Manuals.
Even though there might be a few places they could be improved, I think they're very well written.
-Especially the short "basic configuration"; they serve well as check-lists too.

If you need more than the two I2S channels, you can add the SGPIO, so you easily get 8 channels in or out (perhaps more).

[lpcware]

Content originally posted in LPCWare by acamilo on Sun Sep 15 08:42:25 MST 2013
Whoops, brainfart. i ment i2s not i2c.

Thanks, that answers my question.

[lpcware]

Content originally posted in LPCWare by Pacman on Sat Sep 14 00:23:04 MST 2013
I haven't used the NAU811, nor do I have one, but if you look at the NAU8811 datasheet, you'll find that...

It does not have an I2C interface.
It has SPI interface for controlling the chip; those are CSb, SCLK and SDIO.
It has an I2S interface for transferring the audio: BCLK, DACIN (aka RX_SDA), ADCOUT (aka TX_SDA), FS (aka LRCLK)

Here, you're supposed to use only one BCLK and one LRCLK shared on RX_SDA and TX_SDA.
You cannot intermix with the SCLK and SDIO from the SPI, those are completely different signals and use a completely different protocol. SPI stops when it's no longer being used, while the I2S is supposed to keep running all the time.
You usually don't control the chip very often. Most of the time, that's done during initialization and you might never need to change settings while audio is being transferred.
That said, you could wish to adjust the volume or gain now and then.

So... I'd connect BCLK to a I2S_BCLK, DACIN to a I2STX_SDA, DACOUT to a I2SRX_SDA and FS to LRCLK, then let the LPC4330 be the master.

Alright, back to why you asked the question: You want to avoid a 'short' between I2SRX_CLK and I2STX_CLK, right ?
If you look in the UM10503, Table 954 (page 1085), you'll see:

0x2: Select the TX_MCLK signal as the RX_MCLK clock source.

-That is probably what you want.

Try setting up the circuit and start by transmitting a square-wave to the NAU8811. Check the signal with your scope, and see if the NAU8811 outputs audio.
If it does, you can then setup the receiving part; because you know that the audio-clock is already running and working.

Section 42.7.2 in the UM10503 is worth noticing, try looking at Section 42.7.2.2.3 (table 964, page 1097).
If you don't have them already, I'll recommend downloading UM10503 and the datasheet for LPC43x0.