Why does the following code not jump into ISR?

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Why does the following code not jump into ISR?

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by awinkX on Mon Mar 10 03:25:26 MST 2014
Iam using the LPC1111 with Keil and Ulink Pro

Following Code should jump into ISR with a falling edge on PIO1_5 but nothing happens.


void TIMER32_0_IRQHandler (void)
{
uint32_t irq_reason;

  /* get IRQ reason */
irq_reason = LPC_TMR32B0->IR;

/* capture IRQ event */
if((irq_reason & 0x10)>0)
{

}

/* reset IRQ reason */
LPC_TMR32B0->IR = irq_reason;
}


int main (void)
{

  SystemInit(); //12Mhz internal
 
  /* Enable AHB clock to the GPIO domain. */
  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
   /* Enable clock IOCON */
  LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);


  LPC_IOCON->PIO1_5 = 2| 2<<3 | 1<<5;                     //input/pullup/hysteresis/CAP0

  GPIOSetDir( 1, 5, 0 );                                                //PIO1_5 AS INPUT
  GPIOSetValue( 1, 5, 0 ); 
 
  LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9);                  //enable clock signal to 32 bit timer0

  LPC_TMR32B0->PR=1;                                                    //Prescaler 1
  LPC_TMR32B0->TCR            = 2;                                      // Reset Timer
  LPC_TMR32B0->CCR            =6;                                       //Capture on falling edge, Interrupt enable        

  NVIC_SetPriority(TIMER_32_0_IRQn, 1);
  NVIC_EnableIRQ(TIMER_32_0_IRQn);
 
  LPC_TMR32B0->TCR = 1;                                                 // Enable Timer


while(TRUE)
  {
__NOP();
  __NOP();
   __NOP();

  }  
}

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by awinkX on Mon Mar 10 08:09:29 MST 2014
Solved:
Its a Debug Setting Problem!
-> DEBUGGER SETTINGS-> Connect & Reset Options -> Reset = SYSRESETREQ-> it works
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891件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by awinkX on Mon Mar 10 07:29:27 MST 2014
Could it be that this error is caused by debugger?
When i set a systemresetReq over  Periphals-> NVIC it jumps into ISR
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