When is "AOREG1" (Reset Cause) reset on LPC55S28?

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When is "AOREG1" (Reset Cause) reset on LPC55S28?

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JacobBerggreen
Contributor II

Lately, my team has run into some issues where multiple bits are set in the AOREG1 register.

We've managed to reproduce the problem.

If the controller wakes up from deep power down, bit DPDRESET_WAKEUPIO is set. Then, if we trigger a Watch Dog reset, after reboot both bits DPDRESET_WAKEUPIO and WDTRESET are set.

On the other hand, if we force a "System Reset" (SYSTEMRESET) or a "Pin Reset" (PADRESET) and then trigger a Watch Dog reset afterwards, only the Watch Dog bit (WDTRESET) is set.

The User Manual (UM1126) states that the register is "Reset by: PoR, Brown Out Detectors Reset".

Can you please elaborate on these details?

LPC552x-S2x 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

I see that you have observed that both DPDRESET_WAKEUPIO bit and WDTRESET bit in the AOREG1 register after watchdog resets. I have discussed with the other engineer, we thick it is possible, all the bits in the AOREG1 register are set by software in boot code, so it is possible that the DPDRESET_WAKEUPIO bit is not cleared after watchdog reset event is detected.

Hope it can help you

BR

XiangJun Rong

 

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JacobBerggreen
Contributor II

Hello XiangJun Rong

Can you please confirm that the documentation (UM1126) is incorrect? If so, can you please supply correct information on when this register is actually reset?

Jacob

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JacobBerggreen
Contributor II

Hello XiangJun Rong

Thank you for your answer. Unfortunately, it does not help us.

According to what you state, a Watch Dog reset should execute the Boot code and reset the register. But this is not always what we see.

As stated in my original post, if the DPDRESET_WAKEUPIO bit is set, then a Watch Dog reset will not reset the register (DPDRESET_WAKEUPIO bit is still set after Watch Dog reset).

Please let me know if you need further information.

Regards, Jacob

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Regarding the AOREG1 register, as the section 13.4.13, the AOREG1 register is " managed and updated by the ROM Boot Code.",after each reset, the boot code is re-executed, the  AOREG1 register is updated once based on different Reset source.

The waking up from deep power down will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register.

The Watch Dog reset will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register.

The System Reset" (SYSTEMRESET) or a "Pin Reset" (PADRESET) will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register.

The PoR, Brown Out Detectors Reset will reset the processor and the processor will re-execute the Boot code and update the AOREG1 register. The POR means that the  power-up process will generate the POR reset. The Brown Out Detectors Reset means that when the VBAT_DCDC voltage is less than a threshold voltage, it generate BOD interrupt or reset, but your firmware has to be configured to generate BOD reset.

I copy it from UM11126.pdf

4.6.4 Brown-out detection
This device includes one Brown-out detector to monitor the voltage of VBAT. If the voltage
falls below one of the selected voltages, see Section 13.4.6 “VBAT Brown Out Detector
(BoD) control register” the BOD asserts an interrupt to the NVIC or issues a reset, see
Section 13.4.1 “Power Management Controller FSM (Finite State Machines) status
(STATUS)”.
The interrupt signal can be enabled for interrupt in the interrupt enable register in the
NVIC, see Table 8 to cause a CPU interrupt; if not, software can monitor the signal by
reading a dedicated status register.
If the BOD interrupt is enabled, the BOD interrupt can wake up the chip from a reduced
power mode, not including power-down and deep power-down. See Chapter 14
“LPC55S6x/LPC55S2x/LPC552x Power Profiles/Power Control API”.
If the BOD reset is enabled, the forced BOD reset can wake up the chip from reduced
power modes, not including power-down and deep power-down.

 

I copy it from UM11126.pdf

13.4.13 General purpose always on domain data storage
This register is managed and updated by the ROM Boot Code. It gathers some important
System Status information like the last System reset cause and the number of fatal errors
that occurred during the ROM boot. Though it is readable and writable, it can not be
modified by any application.

 

Hope it can help you

BR

XiangJun Rong

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