Wait 15 seconds for PLL to lock the input from 32KHz Crystal

[koonyook]

I'm working on LPC54102 and I want to change PLL's input from IRC to 32K Crystal for better timer stability.

What I did is to change 1 line of code in sysinit_5410x.c (function void Chip_SetupIrcClocking(uint32_t iFreq))

I change from

Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC);

to

Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_RTC);

and I set in board.h
#define BOARD_MAINCLOCKRATE       (32768000)

When I run, it will take about 15 second (on LPCXpresso54102 board) to wait in this loop (pll_5410x.c)

while (Chip_Clock_IsSystemPLLLocked() == false) {}

The time can even raise up to 4 minutes on my prototype board. (sometimes it just wait forever)

Is there any way to speed up the PLL lock?

I also have found in user manual (UM10850 Rev2.1) page 68 that

"The PLL lock indicator is not dependable when Fref is below 100 kHz or above 20 MHz."

If I cannot depend on the PLL lock indicator, is there any good practice when the PLL input is 32.768 kHz?

[rolfmeeser]

When the reference frequency of the PLL is 32 kHz (i.e. <= 500 kHz) you cannot rely on the lock bit anymore. Instead you should simply wait for a minimum time after enabling the PLL before using its output clock.

The user manual gives a formula in chapter 4.6.4.5.1 for the minimum time to wait when a 32 kHz reference is used (> 6.1 ms). However, I recommend to wait much longer (100 ms at least). The reason is that the 6.1 ms assumes the settings for SELI/SELP/SELR in the PLL control registers are calculated as per the formulas given for the SYSPLLSSCTRL0 register. A remark for 32 kHz operation has been added to the user manual at a later date, recommending fixed values for the SELx fields. These fixed values set a much narrower loop bandwidth, leading to noticeably increased settling time.

P.S.: You define the board clock frequency as "32768000". This is 32.768MHz. Doesn't seem right to me.

P.S.2: Note that the fixed settings for SELx assume you are using the built-in RTC oscillator. This oscillator has significant jitter, which leads to the PLL becoming unstable and losing lock if the calculated SELx filter coefficients are used.

In the unlikely case of applying an external low-jitter reference via CLKIN, using the calculated SELx values is allowed, and a settling time of 6.1 ms may be assumed. I guess this is not your application setup though...

[Carlos_Mendoza]

Hi Prayooc,

Maybe you can use the "LPC5410x PLL setup example" that comes with the LPC54102 LPCOpen package as reference, this example shows how to setup and use the clock driver to generate different PLL rates at run-time. Will switch the main system clock to the safe (IRC) clock, set a new PLL frequency, and then the main system clock to the PLL.

You can download the LPCOpen package from this link:

LPCOpen Software for LPC5410X|NXP

The example is called "periph_pllfract".

Hope it helps!

Best Regards,

Carlos Mendoza

Technical Support Engineer

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------