I am reading through the LPC55xx series User Manuals. I have found some inconsistencies in the documentation and would like to request an update to these User Manuals with clarifications/corrections to these inconsistencies.
The register Type D and A IOCON register bit funtionality descriptions do not match up with the suggested pin settings for various functionality i.e. SPI, UART, I2C, ...
UM11295 LPC55S1x/LPC551x User manual Rev. 1.6 - 6 October 2021
Chapter 15.5.1 Type D IOCON registers on page 348 Table 364 Type D IOCON registers:
--> Bits 31:10 are marked as "Reserved"
35.4 Pin description Table 660 Suggested SPI pin settings:
--> Type D pin suggested settings include:
- Bit #15 = 0 --> I2CFILTER
- Bit #14 = 1 --> EGP
- Bit #13 = 0 --> ECS
- Bit #12 = 1 --> FILTEROFF
- Bit #11 = 0 --> SSEL
- Bit #10 = 0 --> ASW
The suggested settings in Table 660 seem to communicate that the Type D IOCON registers control additional functionality in the Type D pads that are not described in the Table 364. This is inconsistent and confusing. Do Type D pads have additional functionality that can be controlled with these additional bits #15:10?
This finding is consistently found throughout the document also for other pin configurations i.e. UART, SPI, SCT, ...
This finding is consistently found throughout the LPC55xx family User manuals i.e. UM11126, UM11295, UM11424.
Please provide an update to these user manuals with fixes to these issues.
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