Content originally posted in LPCWare by Rob65 on Fri Nov 07 03:19:01 MST 2014
I am reading rev 1.6 of UM10601 recently downloaded from nxp.com and found some errors:
In section 10.6 (page 136) the definition of REGMODEn bits is wrong.Here it is described that a 1 means "match and reload" and 0 is "capture and capture control"
But table 130 on page 146 states the opposite (0 = match, 1 = capture).
Looking at the example it seems that the table is correct.
This makes it very hard to use the SCT. The part is too complex to just use out-of-the-box (yes - because of all the nice features it has).
Another problem arises when we tried to use the Deep power-down mode.
The user manual does not explain that the DPDFLAG in the LPC_PMU->PCON registers must be cleared before entering deep power-down mode.
The manual (see page 66) gives 6 steps with step 2 "Ensure that bit 3 in the PCON register is cleared".
Table 56 (page 59) is referenced and here it is stated that if bit 3 is set, the part deep power-down mode is blocked.
But when the DPDFLAG is not cleared before writing 0x3 into the PCON register to enter deep power-down mode, entering deep power-down mode seems to be locked also.
At least, that is what we noticed while forgetting to clear the DPDFLAG.
Since deep sleep and power down modes are very hard to debug, this made me banging my head against the wall for a few hours before discovering what was missing ...
