Trying to access 8-bit static memory

[lpcware]

Content originally posted in LPCWare by fiosca on Wed Sep 02 02:47:46 MST 2015
We have a board with LPC4357 and many external memories (static and dynamics).
Static memories are connected on:

CS0 --> 32-bit wide NOR Flash
CS2 --> 8-bit wide FRAM

We configured EMC in order to work in 32-bit mode for CS0 and 8-bit mode with CS2.
The NOR flash on CS0 works properly, but the FRAM on CS2 doesn't.
I think there's a problem on how EMC performs access to the bus.

If we write or read one single byte on FRAM everything is fine,
but once we try a 16-bit or 32-bit access, it looks like EMC performs one single bus access (16-bit or 32-bit wide) instead of 2 or 4 read or write cycles.

Just to be clear, this is the problem that can be reproduced with this sequence:

-------------------------------------------------------------------------------------------------------------------
Initial setup:
Write 0x11 to 0x1E000000
Write 0x22 to 0x1E000001 
Write 0x33 to 0x1E000002
Write 0x44 to 0x1E000003

Then I launch some readings:

Read 8-bit at 0x1E000000 --> get 0x11 --> CORRECT
Read 8-bit at 0x1E000001 --> get 0x22 --> CORRECT
Read 8-bit at 0x1E000002 --> get 0x33 --> CORRECT
Read 8-bit at 0x1E000003 --> get 0x44 --> CORRECT

Read 16-bit at 0x1E000000 --> get 0x1111 --> WRONG (it should be 0x1122)
Read 32-bit at 0x1E000000 --> get 0x11111111 --> WRONG (it should be 0x11223344)

It sounds like EMC performs many readings, but the address points always to the first byte.

-------------------------------------------------------------------------------------------------------------------

Connection is quite simple and follows NXP user manual, with full address bus (A0..A12) and only the first byte of data bus (D0...D7).
We don't use byte lanes, only CS, WE and OE standard pins.

Below the configuration of EMC for CS2:

LPC_EMC->STATICCONFIG2  = (1 <<  7) ; /* Byte lane state: use WE signal     */
LPC_EMC->STATICWAITOEN2 = (0 <<  0) ; /* Wait output enable: No delay       */
LPC_EMC->STATICWAITRD2  = 1 + EMC_NANOSEC(70, SystemCoreClock, div);

I already tried to reverse byte lane polarity (even though we don't use byte lane at all!), enabling/disabling page mode and buffers but it has no effect.
Whal could be the reason? Some suggestions?

[lpcware]

Content originally posted in LPCWare by DF9DQ on Mon Sep 14 11:39:57 MST 2015
FRAM's (those that I know) latch the address when a read cycle begins. They cannot deal with the situation where the address (and only the address) changes during the read cycle.

There is no safe way to prevent the LPC4357 from emitting these optimized read cycles (reading words on an 8-bit bus, doing DMA burst access, etc).
FRAM must therefore be considered incompatible with the static memory interface of the LPC4357.

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Sep 14 08:00:22 MST 2015
Can you check if address pins A0 (pinP2_9) and A1 (pin P2_10) are correctly set to function 3?
It could be that the bootcode does not set them for EMC usage, for 32-bit memory these pins are not used.
In principle all CSx can work independently from each other with different memory data width.

Regards,
NXP Support Team

[lpcware]

Content originally posted in LPCWare by fiosca on Thu Sep 03 09:31:16 MST 2015
I found this on the LPC43xx user manual:

"If the external memory is used as external boot memory for flashless devices, refer to Section 5.2 on how to connect the EMC. The memory bank width for memory banks one and two is determined by the setting of the BOOT pins."

Our board boots from external flash on bank 0,  where we have a 32bit NOR flash. It looks like also bank1 and bank2 work at the same bus width and it's not possibile to change it.
Does anybody have any experience about this?