The problem for dual SPI output

[JAY_tang]

I use FC9 SPI as the master device. Send 24 clocks by writing three 8-bit data to the FIFO. The picture below is the clock waveform when sending.

But when I utilize both FC9 SPI and FC3 SPI in the same way, there is a long time gap between 3 8-bit data transmissions.

Below is part of my code

while (1)
{

if((SPI_GetStatusFlags(EXAMPLE_SPI_MASTER) & kSPI_TxEmptyFlag)&&VCC_discharge_flag)
{
EXAMPLE_SPI_MASTER->FIFOWR = 0x74e0008;
EXAMPLE_SPI_MASTER->FIFOWR = m | 0x74e0000;
EXAMPLE_SPI_MASTER->FIFOWR = 0x75e00FC;
m = m + 11;
}

if(m > 0xEE)
{
VCC_discharge_flag=0;
}

if((SPI_GetStatusFlags(EXAMPLE_SPI_MASTER_VCCQ) & kSPI_TxEmptyFlag)&&VCCQ_discharge_flag)
{
EXAMPLE_SPI_MASTER_VCCQ->FIFOWR = 0x7470008;
EXAMPLE_SPI_MASTER_VCCQ->FIFOWR = n | 0x7470000;
EXAMPLE_SPI_MASTER_VCCQ->FIFOWR = 0x75700FC;
n = n + 11;
}

if(n > 0xEE)
{
VCCQ_discharge_flag=0;
}

}

[xiangjun_rong]

Dear Tang

I have read your code, the control part of the FIFOWR register are 0x0x074E, 0x074E and 0x075E, the EOF(End of Frame) bit is NOT set, delay time is not inserted, I think the control code are correct.

From the spi clock signal waveform on the scope, it appears that the square-waveform   clock signal becomes a sine signal, I suppose the SPI clock signal(SCK) frequency is too high, which highlights the gap between two bytes.

Pls try to reduce the spi clock frequency.

Hope it can help you

BR

XiangJun Rong

[JAY_tang]

I hope someone can help me!!!!!!!!Thanks