SSP1 ISR triggered with MIS register = 0x00000000 and RIS = 0x00000008

[lpcware]

Content originally posted in LPCWare by jgorsk on Wed Sep 19 06:05:57 MST 2012
I'm using SSP1 on the LPC4337 in SPI mode. Sometimes (not always) SSP1 interrupt is triggered
with MIS = 0x00 and RIS  = 0x08. IMSC at that time  is 0x00.

I'm sending a train of words over SPI by first preparing a buffer and setting TXIM bit
in IMSC register from my main program. Then a SSP1 ISR is triggered which writes
the word to be sent to SSP1 data register and then clears TXIM disabling SSP1 interrupt.
SSP1 generates CS signal automatically. When SPI transfer is finished the CS signal generates
a pin  interrupt or its rising edge. The pin interrupt ISR generates a few other signals
which latch data in the slave SPI devices. It then sets TXIM to re-enable SSP1 interrupt
and the cycle is repeated.

When the SSP1 ISR is triggered and there is no more data to be sent in my buffer
the SSP1 ISR will just clear TXIM bit.

I can't find a detailed description of how the SSP1 interrupt signals and interrupt
masking work.

There may be something wrong with my program but regardless of that how can an ISR
be triggered with Masked Interrupt Status register being 0x00?

[lpcware]

Content originally posted in LPCWare by jgorsk on Wed Sep 19 13:03:33 MST 2012
The problem is solved. Last line in SSP1_IRQHandler was clearing TXIM bit.
In assembly code it was followed only by 'BX  lr' command. If any other C code
line is inserted after clearing TXIM bit, SSP1 interrupt status bits are working fine
and there are no 'false' SSP1 interrupts.

Before TXIM bit was actually cleared another SSP1 ISR was triggered. ARM architecture
is new to me so I'm not exactly sure why it works that way. Is it becasue of the pipeline
architecture of the CPU or the actual writes to the registers are delayed?