I think the problem is in the maximum frequency compatible with SSP peripheral in LPC1768.
In the Product Datasheet of LPC1768 (here), in chapter 12.7 "SSP interface", I see the following sentence:
The maximum SSP speed is 33 Mbit/s in master mode
It seems it is the maximum bitclock frequency of SCK signal. This explains why my code works at 24MHz, but not at 48MHz.
The SSP bitclock is CCLK/PCLK_SSP0 /(SCR+1)/CPSDVSR, where:
- CCLK is the CPU clock (in my case 96MHz)
- PCLK_SSP0 is the peripheral clock divider (1, 2, 4, 8)
- SCR is 0..255
- CPSDVSR is 2, 4, ... 254
Is there a maximum value for the SSP peripheral clock (i.e., CCLK/PCLK_SSP0)?
To obtain 24MHz bitclock I need to divide CCLK=96MHz by 4. Two possibilities are possible:
- PCLK_SSP0=2; SCR=0; CPSDVSR=2 (SSP clocked at 48MHz)
- PCLK_SSP0=1; SCR=1; CPSDVSR=2 (SSP clocked at 96MHz)
Another question. I could use SPI peripheral instead of SSP0. It seems a completely different peripheral that is always compatible with SPI bus. What is the maximum frequency clock for SPI peripheral? Are there any differences between SPI and SSP0 regarding maximum clock frequencies?