Read PHY registers, got all "0xffff"

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Read PHY registers, got all "0xffff"

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by twicave on Mon Jun 15 22:36:23 MST 2015
I still work on Ethernet module.
the PHY chip what I used is KSZ8041NL.

when I read PHY's register, even PHYID0, PHYID1 register.
what I got is all "0xffff", why?
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thosewhowish2b
Contributor II

To anyone that lands here, I had a similar problem (read 0x0000 on even addresses, 0xFFFF on odd ones) with S32K148EVB+TJA1101-RMII.

The problem was that the pin that drives the reset signal on the mezzanine connector must be configured as well (kinda obvious, but still). This is PTA17, signal PTA17/FTM0_CH6/ENET_RESET to the MCU side of the level converter and ENETSW_RESET to connector side.

I kept comparing my ENET/PHY configuration with the phy_tja1101_s32k148 example from NXP, and they were exactly the same! Turns out, the example silently configures the pin with a default initial value, which holds the PHY out of reset.

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi thosewhowish2b

This is a very old thread of 5 years ago. I am afraid NXP on line support team not monitor it.

Besides, your question is about S32K. I suggest you create a question in S32K space

https://community.nxp.com/t5/S32K/bd-p/S32K

NXP have S32K support monitor the incoming new questions.

 

Best Regards

Jun Zhang

 

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thosewhowish2b
Contributor II

No worries, my problem was already solved when I posted. I just figured someone with the same problem on S32 could land on this page as I did.

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ZhangJennie
NXP TechSupport
NXP TechSupport

Thank you!

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by twicave on Tue Jun 16 02:12:05 MST 2015
have found the reason.
PHY's address configure is wrong.
default value is "001", but the real circuit settng is "101"
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