Power-Down and External Reset Issue

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Power-Down and External Reset Issue

990件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by silex on Fri Feb 20 07:32:14 MST 2015
Hello,

I could make LPC1754 to get into Power-Down mode, but although it is not stated in its user manual, a signal on External Reset pin causes mcu to wake-up. I would like to know if it is usual. If not, how can i prevent wake up from external reset signal?

Thank you.
ラベル(1)
0 件の賞賛
返信
2 返答(返信)

977件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by R2D2 on Fri Feb 20 13:03:27 MST 2015

Quote: silex
...but although it is not stated in its user manual



:quest:

UM10360 Table 73:

Quote:
RESET 14  I
External reset input: [color=#f00]A LOW-going pulse as short as 50 ns on this pin resets the
device[/color], causing I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

0 件の賞賛
返信

977件の閲覧回数
lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by nerd herd on Fri Feb 20 11:38:42 MST 2015
Hi Silex,

Asserting an external reset signal while in a low power mode will reset the MCU, this is typical. I believe the external reset pin is all hardware controlled meaning there is no way to "disable" it.
0 件の賞賛
返信