PLL Block diagram is not in the LPC82x datasheet or manual

[lpcware]

Content originally posted in LPCWare by larsen on Tue Nov 04 14:53:12 MST 2014
It was not before reading the tool http://www.lpcware.com/content/nxpfile/lpc8xx-clock-and-pll-configuration-tool that the significance of the MSEL and PSEL became clear.

It appears that the frequency conversion functionality of the PLL is not described in the datasheet or manual for LPC82x. In the above tool there is a diagram showing the functions inside the PLL. This is very useful and essential information in order to understand that

FCCO = FCLKIN * (MSEL+1) * (1< < PSEL)*2
FPLLOUT = FCCO /(2*(1< < PSEL)) = FCLKIN *(MSEL+1)

Am I right that this information (both diagram and equations) is missing from the datasheet and manual?
If yes, is this the right place to suggest an update of the documentation?

ps: left shift operator wrecks havoc in the formatting, that's why there are to many spaces in 1< <PSEL

[lpcware]

Content originally posted in LPCWare by NXP_Paul on Thu Nov 06 07:04:30 MST 2014
Larsen
Thank you for your feedback.
I will forward your suggestion to our software team.

Paul

[lpcware]

Content originally posted in LPCWare by larsen on Wed Nov 05 09:28:13 MST 2014
Thanks a lot. Don't see how I could miss this.

Now I have the floor I would like to suggest this (little) thing also about the PLL:

In http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc8xx-packages LPCXpresso LPC824 board version 2.13, file "sysinit_8xx.c" It says

void Chip_SetupIrcClocking(void)... and
void Chip_SetupXtalClocking(void)...
/* Configure the PLL M and P dividers */
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 2 = 324Hz
   MSEL = 1 (this is pre-decremented), PSEL = 2 (for P = 4)
   FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 2 = 24MHz
   FCCO = FCLKOUT * 2 * P = 24MHz * 2 * 4 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(1, 2);

I would clear this up a bit to be more readable and without typos..

/* Configure the PLL's M and P dividers for FCLKOUT=24MHz at FCLKIN=12MHz:
   MSEL = 1 (for M=1+MSEL=2), PSEL = 2 (for P = (1< < PSEL) = 4 )
   FCLKOUT = FCLKIN * M = 12MHz * 2 = 24MHz
   FCCO = FCLKOUT * 2 * P = 24MHz * 2 * 4 = 192MHz (which is within FCCO range) */
Chip_Clock_SetupSystemPLL(1, 2);

PS Whats the escape character to avoid the formatter to do special formatting to 2 consecutive < ?

[lpcware]

Content originally posted in LPCWare by NXP_Paul on Wed Nov 05 06:47:24 MST 2014
Hello
The diagram found in PLL calculator is the same diagram you will find in "Fig 5. Clock generation" on page 30 of the User Manual (v1 dated 18 September 2014, http://www.nxp.com/documents/user_manual/UM10800.pdf).  The PLL details can be found in "Fig 7. System PLL block diagram" on page 56.
Please read paragraph 5.7.4 System PLL functional description for more information regarding the PLL.

Paul