PIO0_10 an PIO0_11 open drain pins

[lpcware]

Content originally posted in LPCWare by cpldcpu on Sun Oct 20 05:33:19 MST 2013
I just tried to use PIO0_10 and 11 as digital output pins and found out the hard way that they have open drain output drivers. Am I correct to assume that all other periphericals that can be connected to those pins via the switch matrix would also use the same output drivers? In that case most of the other output functions (e.g. SPI, UART) would not work correctly either?

[lpcware]

Content originally posted in LPCWare by cpldcpu on Fri Oct 25 01:48:35 MST 2013
Just found this at the end of 6.4.6:

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Quote:
Pins PIO0_10 and PIO0_11 operate as high-current sink drivers (20 mA) independently of
the programmed function.

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This should be stated somewhere in the introduction for GPIO.

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Sun Oct 20 09:44:30 MST 2013

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Quote: capiman
There is a foot note in User Manual UM10601 (Rev 1.2 - 14 March 2013) page 316:
"[3] True open-drain pin"
This foot note is attached to PIO0_10 and PIO0_11.

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Yes that's right, I saw that, too. BUT: I still had my doubts, because I'm not a chip designer and I do not know whether it is possible to create a true open drain pin that can still source current. What if the current sourcing element is a pnp (an NXP BISS ;-) ), driven from a n-channel FET? That would be a possibility for a 'true open drain, <= 5V ' that can still source current.
More doubt arise (arose for me at least) in chapter 6.4.6 (cite):

The I2C-bus pins PIO0_10 and PIO0_11 [color=#f00]can be programmed[/color] to support true open drain mode...

No they can't! They're always like that |(

And: can a low pin-count controller affort to 'sacrifice' 2 pins' sourcing capability?

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Sun Oct 20 09:37:49 MST 2013

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Quote: capiman
There is a foot note in User Manual UM10601 (Rev 1.2 - 14 March 2013) page 316:
"[3] True open-drain pin"
This foot note is attached to PIO0_10 and PIO0_11.

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Yes that's right, I saw that, too. BUT: I still had my doubts, because I'm not a chip designer and I do not know whether it is possible to create a true open drain pin that can still source current. What if the current sourcing element is a pnp, driven from a n-channel FET? That would be a possibility for a 'true open drain, <= 5V ' that can still source current.
More doubt arise (arose for at least) in chapter 6.4.6 (cite):

The I2C-bus pins PIO0_10 and PIO0_11 [color=#f00]can be programmed[/color] to support true open drain mode...

No they can't! They're always like that |(

[lpcware]

Content originally posted in LPCWare by cpldcpu on Sun Oct 20 08:04:42 MST 2013
yeah, but for example the pin configuration diagrams suggest them to be a normal GPIO.

Another thing I have always wondered about: Why is the GPIO to pin mapping seemingly random? In most other MCUs (eg STM32, AVR) they are usually in incremental order.

[lpcware]

Content originally posted in LPCWare by capiman on Sun Oct 20 07:32:54 MST 2013
There is a foot note in User Manual UM10601 (Rev 1.2 - 14 March 2013) page 316:
"[3] True open-drain pin"
This foot note is attached to PIO0_10 and PIO0_11.

[lpcware]

Content originally posted in LPCWare by MarcVonWindscooting on Sun Oct 20 06:26:10 MST 2013
Sorry for you to find out the hard way !

That is exactly what I was wondering for a while. Because the manual doesn't state that in a way void of doubt.
Since NXP also offers Open drain emulation pins you never know. It used to be clear on LPC2100 and some others.

And I'm 99% sure the answer to your question is YES.