Not entering Deep power down on NXPLPC55

[Kamilo]

Hi,

I'm currently experiencing the issue that NXPLPC55S28 is sometimes not entering deep power down on POWER_EnterDeepPowerDown API call.

I found in section 14.4 under table 317 of UM11126 rev 2.4 the remark saying "They are restored in case of CPU
retention (deep-sleep and in power-down) or if the low power mode is not entered (for
example, a pending interrupt)." Similar description can be found in vendor library -> fsl_power.cpp. It indicates that pending interrupt might be a cause for not entering low power mode.

It's also important to note that according to ARM specification even while an exception is disabled, it can still reach the pending state. Upon being enabled it will then transition to active.

It brings me to my questions:

1) Are there any specific interrupts which if they are pending can cause not entering low power down mode?
2) Can disabled pending interrupt cause not entering low power mode? If yes, how to handle it?
3) Are there any other conditions which might prevent the processor from going to deep power down.

Thank you for your help in advance!

[Kamilo]

Hi again,
I made a simple application based on which I could confirm that pending external interrupt causes not entering low power mode. E.g. GPIO pin interrupt, among many others.
I cannot confirm if pending System interrupts like SysTick or could cause not entering low power mode? I assumed that technically they can, could you confirm?

To wrap up:

* low power mode is not entered if there is any pending interrupt, section 14.4 in UM11126, rev 2.4
* even while SysTick interrupts or exceptions on NVIC are disabled, they can still reach the pending state

Solution:

* disable all interrupts, section 3.3.1 in UM11126, rev 2.4
     * on all peripherals which had interrupts enabled before going to low power mode
     * system interrupts, like SysTick

* clear pending interrupts before going to low power mode
    * Involves clearing peripheral interrupts on NVIC register and SysTick and PendSV interrupts on SCB register

[Pavel_Hernandez]

Hello, I recommend open an internal case to share the project. 

Best regards,
Pavel

[Pavel_Hernandez]

Hello, I research more information on the RM, could you let me know what kind of peripheral you are using? Maybe could try to read the status of the driver that you are using and saw if have an interrupt pending.

1) Are there any specific interrupts which if they are pending can cause not entering low power down mode?
On the RM mention interrupt pending and some peripherals have this flag.

2) Can disabled pending interrupt cause not entering low power mode? If yes, how to handle it.

Maybe this will be possible if the peripheral has this option.

3) Are there any other conditions which might prevent the processor from going to deep power down.
I recommend follow the app note.

Best regards,
Pavel

[Kamilo]

Hello,

Thank you for your answer.

I use DMA in ping-pong mode. I already tried to read all register to search for pending interrupts. Various interrupts might be pending even though they are disabled. That makes sense according to ARM specification.
Moreover because of the interrupt nature, even if I read interrupt related registers just before going to low power mode, it might happen that new interrupt will come just after it. 
I can observe if I disable DMA interrupts and clear pending DMA interrupts, entering deep power down is more stable.
However, it doesn't answer my question related to NXP provided info, that pending interrupts can cause not entering low power mode. Which interrupts? What is the status of those interrupts (disabled/enabled)? I'm missing clarifications and concrete info in order to make application stable and robust.
I couldn't find any specific information neither in power management description nor in peripheral description

Best regards,
Kamil

[Pavel_Hernandez]

Hello, my name is Pavel, and I will be supporting your case I recommend review this app notes maybe could help you.

LPC55S6x 2x Low-power & Wake-up Optimization

Best regards,
Pavel

[Kamilo]

Hello @Pavel_Hernandez ,

Thank you for your quick reply. I couldn't find relevant information in this Application Note.
As I mentioned, I can see that UM and vendor API mention that pending interrupt can cause not entering low power modes.

I'm observing that issue most likely because of the DMA interrupts. However, it's just an assumption for now. As I mentioned, ARM specifies that an interrupt can be pending even though it's disabled. Hence, just disabling and clearing pending interrupts won't guarantee there is no pending interrupt when we reach POWER_EnterDeepPowerDown.

The description in UM and API is not clear to me, when that situation can happen, and depending on that answer I might also need some clarification what is the suggested way to handle it.

Let me know if you need more clarification. Thanks for your help in advance.