NVIC_EnableIRQ : enables only one interrupt at a time?

[haiomaio3]

Looking at the one of the implementations of NVIC_EnableIRQ, Im wondering how the ISER works ?


<code>   
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}</code>

Calling the above two consequitve times with a different IRQn, will erase the enable of the previous interrupt. Does it mean I can enable one interrupt at a time?


<p><code>   
NVIC_EnableIRQ(8);   // enables IRQ8

NVIC_EnableIRQ(7);   // enables IRQ7 but disables IRQ8 ?!?
</code></p>


Correct, or do I miss something? Am I enabling two IRQs at a time? If yes, how is it possible, if ISER[0] would contain only the last assignment....

Further, can I set an IER of a peripheral device without enabling its interrupt ?!?

For example, can I set the IER below


<p><code>   
LPC_UART3->IER = 0x00000005UL;            // Enable UART3 interrupt RBR ans RLS

</code></p>

without calling before it   


<p><code>


NVIC_EnableIRQ(UART3_IRQn);

</code></p>

Where do I need to use


<p><code>   
NVIC_EnableIRQ

</code></p>

and/or where do I need to set the corresponding peripheral



<p><code>
IER
</code></p>
?

If I want to enable multiple IRQs over UART->IER simultaneously, I have to do the following ?


<p><code>
NVIC_EnableIRQ(UART3_IRQn);

PC_UART3->IER = ...

NVIC_EnableIRQ(UART2_IRQn);    // this disables UART3 already

PC_UART2->IER = ...
</code></p>


So, what happens with the NVIC UART3_IRQn respectively with the PC_UART3->IER, if the NVIC_EnableIRQ(UART2_IRQn) disables the UART3_IRQn? Do I have to poll the UART3->IER than?

Why is this connection not specified / stated clearly in the specification ?

[carstengroen]

You need to read about the NVIC peripheral for the processor you are working on.....

The ISER register:

(Hint: setting a bit in this register enables the interrupt for this one only, all other interrupts are NOT affected, same with ICER register)

[haiomaio3]

Where do you infer your hint from above from ? Are you talking about NVIC_EnableIRQ at all?

The fist part of the question is setting ISER with the NVIC_EnableIRQ? And the second part is what is the relationship between the ISER and UART->IER registers ?

Btw. the spec I'm referring to is

UM10360
LPC17xx User manual
Rev. 01 — 4 January 2010

[jeremyzhou]

Hi Hai Maio

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
To provide the fastest possible support, I'd like to suggest you refer to the attachment to learn the detail informaiton about the NVIC.

Have a great day,
TIC

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[haiomaio3]

Could you please be more specific? Which sentence in the document, gives an answer to the question from above ?

[jeremyzhou]

Hi Hai Maio

Chapter 6 Nested Vectored Interrupt Controller

Have a great day,
TIC

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[haiomaio3]

Please, give me exactly the sentence, giving the answer. Id red the chapter before your post.