Content originally posted in LPCWare by andrewchen on Wed Apr 16 09:12:58 MST 2014
Hi Friend,
I have some trouble on debug MT48LC4M32B2975,Could anybody give me hand?thanks.
config.ChipSize = 128;
config.AddrBusWidth = 32;
config.AddrMap = EMC_ADD_MAP_ROW_BANK_COL ;/*EMC_ADD_MAP_BANK_ROW_COL ;*/
config.CSn = 0;
config.DataWidth =32;
config.TotalSize = SDRAM_SIZE*8;//SDRAM_SIZE = 0x 1000000;
config.CASLatency= 3;
config.RASLatency= 3;
config.Active2ActivePeriod =3;
config.ActiveBankLatency =10;
config.AutoRefrehPeriod = 3;
config.DataIn2ActiveTime =2;
config.DataOut2ActiveTime = 1;
config.WriteRecoveryTime = 1;
config.ExitSelfRefreshTime = 3;
config.LoadModeReg2Active = 0;
config.PrechargeCmdPeriod = 0;
config.ReadConfig = 1; // Command delayed strategy, using EMCCLKDELAY
config.RefreshTime = 0x2E;
config.Active2PreChargeTime = 2;
config.SeftRefreshExitTime = 3;
dwtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x32<<12))); /* Mode Register Setting: 4 burst, 3 CAS latency */
LPC_EMC->DynamicConfig0 = 0x00004500;
above is config for SDRam and following is troubles.
1)Bank0 (A0000000~A03fffff) cofuse with Bank1 (A0400000~A07fffff) ,and Bank2(A0800000~A0bfffff) confuse with Bank3(A0c00000~A0ffffff).That means when write into Bank1,it would cover Bank0 before writed .The same as bank2 and bank3.it look like the EMC_A13 can not work well.But I check EMC_A13 well by GPIO function.i almost can sure that hardware OK.
2)if it write a single bank ,and then verify time and time.all is pass.if firstly write bank0 ,secondly write bank2 and then verify bank0,it will fail at every sector from 0xaXXXn400 to 0xaXXX(n+1)000. From 0xaXXXn000 to 0xaXXXn3fff is verify pass. Even if secondly not write bank2 but verify bank2,it also get the same result.
I not sure if the problem exist in address map or sdram refresh. Could anybody help me? thanks!
