LPC812 PLL: Why the FCCO output is limited to 156 MHz to 320 MHz ?

[karthikvenkates]

Hi,

I have been trying to understand how the PLL works in LPC812.

I understand that PLL gets the reference clock, does Phase detect, Frequecny detect, Low pass filtering, Current controlled oscillator with a multiplier on the feedback path.

When my reference clock is 12MHz and I want 60 MHz Main clock, I know that FCCO should be 240MHz, M=5, P=2

My question is, who or what decides the FCCO 240MHz frequency ?

Only known parameters are Reference clock = 12 MHz and Main clock = 60MHz (which is desired output from PLL).

Based on these two parameters, I can deduce what the value of M, P and FCCO.

But why the FCCO is limited to 156 MHz-320 MHz range ? What restricts its range ?

Who instructs the CCO to generate 240 MHz for my case ?

Please clarify.

[marcprager · Accepted solution]

An intuitive answer might be:

> My question is, who or what decides the FCCO 240MHz frequency ?

The M value isn't selectable, because it's simply the ration between input pll_in and output frequency pll_out.

P values are powers of 2  and the FCCO range is also nearly 1:2 (156:320) which implies, that for most output frequencies there's exactly one possible value for P. This one possible P decides FCCO = pll_out*2*P. For all the multiples of 12MHz (IRC) this holds true - unique P.

So if using 12MHz pll_in choose the smallest 2P from { 2,4,8,16 } such that pll_out*2P >= 156MHz and that's the only valid 2P :-)

If however you decide on a 80MHz main clock (corner case value), perhaps from a 20MHz input, then you have 2 solutions for 2P/FCCO as follows: 2*1/160MHz and 2*2/320MHz. In this situation, its YOU who decides about the FCCO ;-)

Marc

[karthikvenkates]

Marc,

You mean to say 'P' decides the value of FCCO, right ? Does that mean, the Current controlled oscillator inside, refers 'P' value too ?

See, for CCO, it will take the negative feedback via 'M' as an input and compare it against the reference clock, which is in my case 12 MHz. Based on the frequency difference & phase offset, it will create current which generates correct frequency which is FCCO.

So, how can we say that value 'P' helps CCO decide on its output frequency ?

Moreover, the purpose of the CCO, as I understand should be to detect the Phase and Frequency of the input reference clock. So ideally I should be getting exactly 12MHz as FCCO. But why we are getting 156-320MHz ? PLL halps us get multiples of reference clock, that I understand. But my doubt is which how that happens. If we say 'P' or 'M' plays a role, my question is CCO inside refers either 'P' or 'M' and decides its output frequency. Is that right ? Lets us rule out role of 'M' first. 'M' is determined straightaway from what is the output of PLL we desire. In my case, I desire 60MHz as PLL output. So 60MHz/12MHz = 5 is my 'M'. This is clear. Which means 'M' does not play any role in deciding FCCO.

Which leaves us only one possibility that is 'P'. For 'P' since PSEL can hold only powers of 2, only 4 values are possible - 1,2,4,8 as given in datasheet. So does it say that there is only 4 difference FCCO possible ? 168, 192, 240, 288. OK, now I understand. So CCO refers P and decides whether FCCO should be 168 MHz /192 MHz/ 240MHz/ 288MHz. I got it.

Thanks Marc , Dzheng !

[Dezheng_Tang]

Section 5.7.4.4 Frequency does mention that, hopefully, below

formula makes more sense to you. If you configure FCCO outside

the specified range in PLLCFG, lock won't happen. 

The PLL output frequency (when the PLL is active and locked) is given by:

pll_out_clk = M * pll_in_clk, or  pll_out_clk = FCCO / (2*P)

The CCO frequency can be computed as:

FCCO = pll_out_clk*2*P, or FCCO = pll_in_clk*M*2*P

The PLL inputs and settings must meet the following criteria:

• M is in the range of 1 to 32.

• P is one of 1, 2, 4, 8.

• pll_in_clk is in the range of 10 MHz to 25 MHz.

• FCCO is in the range of 156 MHz to 320 MHz.

• pll_out_clk is in the range of 9.75 MHz to 160 MHz.