LPC55xx ADC interrupt routine

[ianbenton]

Would I be correct in thinking that the interrupt routine should clear STAT[TCOMP_INT] ?

Without doing so the interrupt routine runs continuously. I don't see any statement to that effect in the manual.

[danielholala]

Hello,

That was helpful, even 5 years later.

I'm using multiple ADC channels on the LPC55xx. The ADC FIFO is read out when the ADC interrupt fires. I'm using the FIFO watermark interrupt (FWMIE0). Regarding interrupt status bits, I do not have to reset any flags in the ADC status register as they (e.g., RDY0) apparently get reset automatically as soon as the FIFO has been read out completely.

Today I changed the code from FWMIE0 to Trigger completion interrupt ("TCOMP_IE") and my ISR ran continously, as you observed. So to fix this, after reading out FIFO, I have to clear  TCOMP_INT bit in the ADC status register by writing a 1 to this bit:

ADC0->STAT &= 1U << ADC_STAT_TCOMP_INT_SHIFT;

I wish NXP would put more effort, time and people to work on the documentation. I'm glad we have this community here.

Thanks
Daniel

[frank_m]

I would suppose any set interrupt flag would cause a continuous interrupt execution. The only difference is, certain flags like result ready get reset automatically on reading the result register.

I use to start out with an interrupt handler that clears all enabled interrupt flags regardless of their status.

[Alice_Yang]

Hello,

STAT[TCOMP_INT] is for trigger interrupt flag, not ADC result ready interrupt flag.

If you want to use ADC trigger interrupt, yes, you need write 1 to clear it.

About read ADC data interrupt function, please refer to ADC interrupt demo under  SDK.

Strongly recommend you debug and run the ADC demo first.

Thanks.

BR

Alice

[ianbenton]

When the SDK creates a project, it creates over 60,000 lines of code. I have searched for ADC0_IRQHandler in most of the logical places it could possibly be, but can't find it.

[Alice_Yang]

Hello,

For example lpadc_interrupt demo:

BR

Alice