LPC55S6x/S2x/2x DMA request source - SPI?

[davenadler]

Looking at the LPC55S6x/LPC55S2x/LPC552x User manual (Rev. 1.9 — 15 November 2019).
For each DMA channel, the dedicated DMA request sources are shown in Tables 408 and 409.

These tables are a bit confusing, for example DMA0 channel 4 shows request source
     Flexcomm Interface 0 RX / I2C Slave

Assuming one is not using I2C, does this mean the DMA channel can be used for any flexcomm interface 0 RX function (ie SPI if flexcomm 0 is configured for SPI)?

Thanks!
Best Regards, Dave

[davenadler]

PS devel@latke.net - This is in reference to this question:   https://community.nxp.com/message/1291511 
Any ideas? I've got a couple but not sure. NXP has been unhelpful so far unfortunately...

[devel]

Dave Nadler wrote:

PS Andy Peters - This is in reference to this question:   DMA for Flexcomm SPI with 20-24-bit peripherals? 
Any ideas? I've got a couple but not sure. NXP has been unhelpful so far unfortunately...

Honestly, I can't help with that. I haven't delved into SPI and DMA yet (but it's on my list).

I just spent a good part of my evening yesterday trying to get a simple USART interrupt to work. Turns out that the stupid library had an override for the default handler and so it ignored my override handler. I had to comment out the override in fsl_flexcomm.c -- it's just daft and overcomplicated. I don't even know why it was using fsl_flexcomm.c.

[devel]

Assuming one is not using I2C, does this mean the DMA channel can be used for any flexcomm interface 0 RX function (ie SPI if flexcomm 0 is configured for SPI)?

I'm now working through using DMA with a UART -- the example code and driver are mindbendingly undocumented.

Based on the example lpcxpresso55s28_usart_dma_transfer, the DMA channels are associated with all configurations of a Flexcomm. 

There are two requests for each Flexcomm: one for transmit, the other for receive. When configured to work as I2C, one of the requests is for when the Flexcomm is used as an I2C slave, and the other is used when the Flexcomm is used as an I2C master.

So for Flexcomm 0, the table lists:

 DMA Channel 4: Flexcomm Interface 0 RX / I2C Slave

 DMA Channel 5: Flexcomm Interface 0 TX / I2C Master

It's the same for the other Flexcomms.

There are a couple of examples that use the Flexcomm as an SPI master or slave using DMA transfers.

[davenadler]

I'm finding the documentation very difficult, in particular the following writing mistakes:

1. The term 'trigger' is used completely ambiguously for many purposes, where it is normally meant to be an input and/or event. NXP documents use trigger sometimes as a DMA input and sometimes an output. DMA inputs that start the DMA are more usually called requests. I've never seen DMA completion events called a 'trigger' by anyone except NXP. At a minimum 'trigger' should always be disambiguated: use DMA trigger input or DMA complete output signal.
2. Similarly 'chaining' is used ambiguously. Should always be either DMA buffer chaining or DMA channel chaining. Reference manual usually uses 'linked transfers' for buffer chaining which is better, some of the other docs are more confusing.
3. The semantics of DMA completion signal are not documented anywhere I can find. Presumably it is signaled on 'transfer count counted down to 0 and last transfer finished' but I'm not sure in the context of buffer chaining (what happens during ping-pong?).

Anybody at NXP, can you please request these document clarifications/corrections?

Thanks!
Best Regards, Dave

[Omar_Anguiano]

Hello Dave Nadler

Regarding the documentation, thank you for letting me know, I will inform your comments to the corresponding team.

I apologize for the inconvenience this is causing you, please let me help you clarifying these points to you:

• The "trigger output" is a signal of the channel that can be used as input trigger for another DMA channel. The DMA requests are connected to a peripheral, these requests go through a multiplexer where they are associated with a trigger. This image may help to understand this:

• The main difference of the channel chaining and linked transfer are the descriptors. A linked transfer can use any number of descriptors to define a complicated transfer, on the other hand, the channel chaining allows us to start the transfer of a channel when another channel just completed its operations without CPU intervention.

•  Under Table 435 we have the Channel control and status register, the TRIG  bit can be used to indicate the transfer status. This bit is cleared at the end of an entire transfer or upon reloading when CLRTRIG = 1.

Please let me know if this is helpful, if you have more questions do not hesitate to ask me.

Best regards,

Omar

[davenadler]

jeremyzhou‌ - Can you clarify? You seem to be expert on DMA on these parts?
Thanks!