LPC55S69 : reboot to ISP mode

[EugeneHiihtaja]

Hi !

Cal LPC55S69 reboot to ISP mode itself ?

I mean ISP boot pin is set to Low state externally, Core0 execute System reset and via reboot it start to stay in Bootrom and wait update package.

Some SRAM memory can stay untouched ?

If Core1 code is executed from SRAM, it can continue execution after System Reset as well.

Some SRAM areas what is not used by Bootloader can keep their context as well.

Or after System reset only RTC registers is untouched ?

Or hoe to keep Core1 running while ISP update  and have posibility to reboot to ISP and return back and keep Core1 running from SRAM at at the same time ?

Regards,

Eugene

[ZhangJennie]

HI Eugene

The bootloader code is executed every time the part is powered-ON, is reset, or wakes up from a deep power-down while in a low power mode. So when MCU executes system reset and detects the related ISP pin low, it can go into ISP boot mode.

If you don’t power off MCU, just reset, RAM content keeps there. BUT, after reset, the code re-enter startup code, which includes initialize RAM and zero fill bss segment, etc. if you don't want this initialization, you need bypass this initialization code to avoid previous RAM content being overwritten.

Have a great day,
Jun Zhang

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[EugeneHiihtaja]

Hi Jun Zhang !

You mean reset is not change RAM but it reset all Cores ?

Can core1 continue to run over reboot. 

And after reboot can Core0 identify if it run already ?

Core 0 can restart it quickly if need.

But it is really not clear from UM what kind of type of reset can be executed if Core1 remains ON while ISP is ongoing in Bootloader.

And what kind of SRAM areas can be used, what Bootloader is not touch.

Regards.

Eugene

[ZhangJennie]

Eugene,

>>reset is not change RAM but it reset all Cores ?

yes

>> And after reboot can Core0 identify if it run already ?

no, unless you manually set a flag in flash before reset. 

when reset, core0 is run from start, core1 is booted by core0, so core1 is also restart.

Have a great day,
Jun Zhang

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[EugeneHiihtaja]

Hi Jun Zhang !

I mean can Core continue to Run over reboot ?

When Core0 starts , Core 1 is already running and Core0 can but not mandatory to restart it.

I can allocate SRAM slot what is updated by Core1 periodically and Core0 will know Core 1 state.

But I need Core1 running while ISP update for cover time after Core 0 reboot to bootrom and starts again.

Regards,

Eugene

[ZhangJennie]

HI Eugene,

>> Core continue to Run over reboot ?

When core executes reset, it can't continue running at the code where it quit. the code must start from beginning.

this is different from the low power mode. for example, if the code goes into sleep mode and wait up again, the code must continue running from the place where it stops.

Have a great day,
Jun Zhang

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[EugeneHiihtaja]

Hi Jun Zhang !

So it is not possible to reset just Core0 and start to execute Bootrom and ISP again and leave Core1 running ?

I assume Core1 is occupy free SRAM what is not touched by Bootloader and Secure gate settings is also OK.

Is this so ?

Does BootRom have some hooks what can be used for execute some custom code ?

Can Core0 jumps to Bootloader starts address and forcibly activate ISP mode for some dedicated interface ?

It looks like as not a reset and Core1 should remains if it not touched ?

Or is any other way exists to have Core1 running while ISP update or I should start to think about IAP type of update

but it reduce code space twice.

Regards,

Eugene

[ZhangJennie]

Eugene,

I don't think it's possible.

when LPC is running ISP boot code, neither core0 nor core1 can run application code parallel.

The jump doesn't work also, because we don't know boot rom code function address.

Have a great day,
Jun Zhang

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