LPC55S69 power rise issue, please help to revise the PCB design

[vyacheslavguzhv]

According to the LPC55S6x Errata sheet, the clause 3.26 VBAT_DCDC.1: The minimum rise time of the power supply must be2.6 ms or slower for Tamb = -40 C, and 0.5 ms or slower for Tamb = 0
C to +105 C.

The customer design for the power supply circuits is exactly the same as on NXP LPC55S69-EVK board.

Please kindly suggest how the circuits should be modified in order to meet the errata requirements for 0,5 ms rise time and 2,6 ms rise time. Apriori customer's PCB take the power from external device designed by other companies. Its hard to predict the parameters of external DCDC, therefore lets assume external DCDC rise time is almost immediate. 

thanks!

Slava

[ZhangJennie]

Hi Slava

We recommend to use LDO/DCDC with soft start function which can control the start up time, for example, RT8272, AP62200 series and etc. This will make the power supply circuit simple.

Have a nice day,

Jun Zhang

[ZhangJennie]

 vyacheslavguzhv

We are checking this internally. Will keep you informed.

Thanks,

Jun Zhang