LPC55S69 : handling individual GPIO pins from different Cores

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LPC55S69 : handling individual GPIO pins from different Cores

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EugeneHiihtaja
Senior Contributor I

Hello !

I'm looking for efficient way to handle individual GPIO pins from different Cores.

If pin is allocated to some peripheral role it is there.

But after that remains individual pins in Bank 0 and 1 what should be controlled from Core 1 or Core 0.

So the same pin is clearly used only from one Core but due common registers it might be problem

to read state of PIO1_9  state and change ouput value of PIO1_10 from other Core.

From other side all registers are 32 bit wide and it can be atomic operation to read or write one 32 bit register.

If pins grouped to GINT0/1 or PINT it might be not a problem because the controlled via other peripherals blocks.

But what can be problem to handle individual GPIO pins in one Bank from different Cores ?

Regards,

Eugene

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Sabina_Bruce
NXP Employee
NXP Employee

Hello Eugene,

From what I understand you would like to control GPIO1_9 with core 0 and GPIO1_10 with core 1. You are able to access different pins from different cores individually. However be careful no to attempt to use the same pin at the same time this may cause some issues in your application.

In addition, reading the GPIO1_9 should not affect the pin next to it, so it should not be a problem of changing the value on accident.

The grouped GPIO pins have a specific purpose to work as an interruption.

If you need examples of how to initialize pins on different cores let me know.

Best Regards,

Sabina