LPC55S69 Secure Fault Handling

[__marvin__]

Hi,

I'm currently encountering a problem with secure fault handling and semihosting on LPC55S69.

I'm basically trying to access the secure memory (SECURE_CODE_START) directly in order to generate a SecureFault and analyze it afterwards.

First of all, I was wondering why an occouring SecureFault seems to trigger a HardFault and is not being handled by the SecureFaultHandler routine. (Please correct me in case I'm wrong)

When overwriting the HardFaultHandler as it is given in the LPC55S69 example (SECURE_FAULT_S/NS), my code stops working when not under an active debug section. I assume that there is something messed up with the semihosting, which has been handled by the previous HardFaultHandler.

Thanks a lot && all the best,
__marvin__

[Alice_Yang]

Helllo marvin,

Yes,  the SecureFault has been handled by the previous HardFaultHandler, because HardFault has higher priority than any exception.  About detail, you can have a look at  ARM Cortex-M33 User Guide:

https://developer.arm.com/documentation/100235/latest 

BR

Alice

[__marvin__]

Hi Alice,

thanks for pointing me in the right direction.

Best,
marvin