LPC55S69: CPU lockup while accessing to SYSCON

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LPC55S69: CPU lockup while accessing to SYSCON

886 次查看
raz3l
Contributor III

Hi everyone,

I'm running Zephyr (compiled as Non-Secure) on an LPC55S69, flashed at address 0x0. To boot it, I:

  1. Flashed the NS image at 0x0

  2. Manually set the PC via GDB

The system only works if I comment out this clock initialization line:

CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);

Otherwise, it triggers a processor LOCKUP without any visible exception details. I have checked that SAU and MPU are disabled and I have reviewed the Secure AHB Controller (no obvious blocking configurations).

  1. Could a platform-level firewall (e.g., peripheral access control) block this clock register?
  2. Are there other hardware protections I might have missed?

Thanks!

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842 次查看
Harry_Zhang
NXP Employee
NXP Employee

Hi @raz3l 

Yes, the LPC55S69 has platform-level security mechanisms that could be restricting access to the clock registers when running in Non-Secure mode.

BR

Harry

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835 次查看
raz3l
Contributor III

Hi @Harry_Zhang ,

 

Could you point me to which platform-level security mechanisms are you referring to?

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795 次查看
Harry_Zhang
NXP Employee
NXP Employee

Hi @raz3l 

On the LPC55S69, the platform-level security mechanisms that control peripheral access between Secure and Non-Secure worlds (enabled by ARM TrustZone-M)

Secure AHB Controller (SECURE_AHB / AHB_SECURE_CTRL)

Security access rules for AHB peripherals
Security access rules for AHB peripherals on AHB Slave Port P8. Each peripheral can
have independent security attribute.

Registers: SEC_CTRL_AHB_PORTx_SLAVEy_RULE
These determine whether each peripheral (e.g., SYSCON, CLOCK, IOCON, GPIO) is accessible by:
You can try to test it.

BR

Harry

670 次查看
raz3l
Contributor III

Thanks!

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