LPC55S16 AHBCLKDIV Problem

[berndsirozynski]

LPC55S16 AHBCLKDIV Problem

i wonder that my core frequency is not correct and found that the value in the

AHBCLKDIV register is 0x1 after reset. this means the divisor is set to 2

The user manual says: the default value after reset is 0x0

so i set this register to 0 to set the divider to 1

if i do this, my CPU stopped.

if i set the divider to 2 the the clock is divided by 3, that works fine

if i set the divider to 1 the the clock is divided by 2, that works fine

but i cant set the value to 0

CPU stopped

Bernd

[berndsirozynski]

The Problem was resolved:  The Reset Value is wrong

The register MAINCLKSELA is on 0x3 after a reset
and thus on FRO 96 MHz clock.
According to the data sheet it should be at 0x0 12 Mhz after a reset

Solution:
If I write 0x00 in the MAINCLKSELA, i.e. FRO 12 MHz, then I can
Set register AHBCLKDIV to 0.
My clockout is then 12 MHz and instruction cycle 83ns ==> 12 MHz
so it works properly.

[ZhangJennie]

HI

According to LPC5516 UM, when AHBCLKDIV:DIV is 0, clock is divided by 1, when DIV is 1, clock is divided by 2. 

Have a great day,
Jun Zhang

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[berndsirozynski]

Hello Jun Zhang,

first thanks for your answer.

The problem is, that you cant set the "DIV" value to zero.

if i do that, i get an BUS fault error.

the default value after reset is "1"

Bernd

[ZhangJennie]

I have tested, use below code inside board clock initialization code can set AHBCLKDIV as 0 without issue.

 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 0U, false);         /*!< Set AHBCLKDIV divider to value 0 */‍

Have a great day,
Jun Zhang

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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