I would like to test burst transfer based on the DMA channel chain transfer example in the SDK, but the example seems to behave like burst transfer with single transfer (default).
I understand the number of transfers per request or trigger as follows:
If software trigger is used (SWTRIG=1), transfers are performed until descriptors are exhausted (RELOAD=0) or trigger is cleared (CLRTRIG=1).
If DMA request is used (PERIPHREQEN=1), a transfer is performed per request.
If hardware trigger is used with edge trigger (HWTRIGEN=1, TRIGTYPE=0), a transfer is performed per trigger with single transfer (TRIGBURST=0) or the number of transfers defined by BURSTPOWER is performed per trigger with burst transfer (TRIGBURST=1).
Is my understanding correct?
The DMA channel chain transfer example in the SDK seems that transfers continue until the descriptor is exhausted with the single transfer.
I have contacted TIC support about this.
I modified the DMA channel chain transfer example for HW trigger and tested it, it seems that transfers by per trigger with single transfer (TRIGBURST=0) are performed until descriptors are exhausted (RELOAD=0) or trigger is cleared (CLRTRIG=1).
Why do the single transfer show this behavior in the example?
The modified example source code is attached.
HW trigger connection in the modified example:
PINT (P1_9 to low by S3 on LPC55S28-EVK) -> DMA0CH0 -> DMA0CH1 -> DMA0CH2
On the other hand, it worked as expected with burst transfer (TRIGBURST=1).
Hello, my name is Pavel, and I will be supporting your case, let me review your case and when I have more information, I will contact you.
Thank you for your reply and daily support.
I would appreciate it if you respond to my case in TIC instead of this case.
I saw you have 3 cases with some differences in the DMA, for quality of service I will be following your case in one of these.