LPC55 - CAN base address alignment

[MRota]

Hi,

I am following up from this question
Solved: CAN base address align restriction in LPC55 - NXP Community

Recap:
- The CAN0_RAM_BASE_ADDRESS is linked into the .bss section.
- The .bss output section comes after the .data output section, and both are linked into the RAM_0_1_2 (0x20000000). This RAM has a lenght of 0x10000.
- So, if .data is not empty, CAN0_RAM_BASE_ADDRESS can not be linked into the address 0x20000000 because it is already use by .data vars, and the following address aligned to 0x10000, is 0x20010000, and unfortunetly is out of range of the RAM_0_1_2.

The provided workaround was:

SDK_ALIGN(uint32_t CAN0_RAM_BASE_ADDRESS[CAN0_MESSAGE_RAM_SIZE], CAN0_BASE_ADDRESS_ALIGN_SIZE) = {1};

But while this works, there is something in the autogenerated comments that... well

/* Allocation of the Message RAM in memory that is alligned to 16 bits. */
SDK_ALIGN(uint32_t CAN0_RAM_BASE_ADDRESS[CAN0_MESSAGE_RAM_SIZE], CAN0_BASE_ADDRESS_ALIGN_SIZE);

 

Aligned to 16bits? 0x10000 is 64Kb.
If the autogenerated comment is true, the alignment should be 0b10000.

[Alice_Yang]

Hello @MRota 

Thanks for contacting us. There might be some confusion about the term "aligned to 16 bits." It actually means that the memory address must be aligned on a 16-bit boundary.  For example, valid addresses include 0x10000, 0x20000, 0x110000 and 0x20010000 — in each case, the last 16 bits of the address are the same.

In other words, the memory space 2¹⁶  is 64 KB.

Thank you.

BR

Alice