LPC54S018J4MET180 ethernet MDC signal conflicts with EMC

[liangliangma]

We are going to use LPC54S018J4MET180 to provide an ethernet interface with 32MB SDRAM.

With MCUXpresso Config Tools v13.0 to configure the peripheral signals, it seems the ENET MDC pin conflicts with the EMC D2 or A10 signal. Then how to use the ethernet interface and SDRAM together?

[hfuhruhurr]

Hi all,

a somewhat late response or rather a question to this issue:

Assume that some occasional access to the PHY is necessary, e.g. to put it asleep, check connection stats, etc.

Would it be possible / considered as good behaviour to prevent SDRAM access for these short periods?

E.g. In a FreeRTOS project, the PHY access could be put into a critical section.

Best regards,

Rainer

[xiangjun_rong]

Hi,

Regarding your question, you use LPC54018J4MET180, it is 180 pins TFBGA package.

This is the ENET_MDC pin assignment, pls check if you can allocate it.

PIO0_4 C8 pin ENET_MDC

PIO1_16 B7 pin ENET_MDC

Pls download data sheet of LPC540xx and check the pin assignment.

If you do use PIO0_4 pin as both ENET_MDC and EMC_D(2), I suppose it is okay. You can configure the pin as ENET_MDC or EMC_D(2,), when you start the ethernet to communicate with PHY, configure the pin as ENET_MDC, after the PHY communication is complete, you can configure it as EMC pin.

If it is possible, you'd better use independent pin for ENET_MDC function.

Hope it can help you

BR

XiangJun Rong

[rijn]

Hi there

i have the same problem

MDC is required as a continues clock provided by STA.

and at the same time all data obtained via ethernet will be stored on EMC_DRAM.

i suppose no workaround on this ?

[xiangjun_rong]

Hi,

The ENET_MDC/ENET_MDIO pins are used to configure the PHY, so the ENET_MDC clock is required only when you configure PHY, it is not a continuous clock, when the configuration is over, the two pins are not used, you can configure it as SDRAM pin.

Hope it can help you

BR

XiangJun Rong

[liangliangma]

You have to either use LPC54S018JET180 instead, or emulate the MDIO interface with SPI, by connecting SPI SCK to phy MDC signal, configure MOSI to open drain output, connect MOSI and MISO togather to phy MDIO, then you can read/write via 16bits SPI transfer. Remember to add a pull up resistor on the MDIO signal, which I think is required by most of the phy chips

#include "fsl_spi.h"

#define MDIO_START 0x4000u
#define MDIO_WRITE (MDIO_START | 0x1002u)
#define MDIO_READ (MDIO_START | 0x2003u)

int mdio_read(int addr, int reg)
{
uint16_t cmd = MDIO_READ | (((uint16_t)addr & 0x1fu) << 7) | (((uint16_t)reg & 0x1fu) << 2);
uint16_t cmdbuf[4] = {
0xffffu, 0xffffu, cmd, 0xffffu
};

uint16_t buf[4] = {0};
spi_transfer_t xfer = {
.txData = (void *)cmdbuf,
.rxData = (void *)buf,
.dataSize = sizeof(cmdbuf),
.configFlags = kSPI_FrameAssert,
};
status_t status = SPI_MasterTransferBlocking(SPI9, &xfer);
if (status != kStatus_Success) {
return -1;
}

return buf[3];
}

int mdio_write(int addr, int reg, uint16_t val)
{
uint16_t cmd = MDIO_WRITE | (((uint16_t)addr & 0x1fu) << 7) | (((uint16_t)reg & 0x1fu) << 2);
uint16_t cmdbuf[4] = {
0xffffu, 0xffffu, cmd, val,
};

uint16_t buf[4] = {0};
spi_transfer_t xfer = {
.txData = (void *)cmdbuf,
.rxData = (void *)buf,
.dataSize = sizeof(cmdbuf),
.configFlags = kSPI_FrameAssert,
};
status_t status = SPI_MasterTransferBlocking(SPI9, &xfer);
if (status != kStatus_Success) {
return -1;
}

return 0;
}

[liangliangma]

Really please read my question and the LPC54018JxM/LPC54S018JxM datasheet again. We need the hash and encryption coprocessor, that means we cannot use LPC54018

[xiangjun_rong]

Hi,LiangLiang,

Okay, I see that you use LPC54018JxM/LPC54S018JxM.

Both of the PIO1_16 and the PIO0_4 pins are multiplexed with EMC, if you use both EMC and Ethernet, one pin must function both.

I suppose that the ENET_MDC is a low speed signal, but the EMC_D2 is a high speed signal, when you design PCB, you have to consider the signal integrity feature.

Hope it can help you

BR

XiangJun Rong