LPC546xx SCT: PWM with a duty-cycle of 0% in Edge Aligned mode

[giusloq]

I'm trying to use SCT peripheral for a simple PWM output.

I started from lpcxpresso54628_sctimer_simple_pwm SDK example project for EVB OM13098 and it works, I saw 24kHz PWM with 50% duty-cycle.

I made the following changes:

• commented out the second call of SCTIMER_SetupPwm() to avoid conflicts with the first
• changed counter mode from kSCTIMER_CenterAlignedPwm to kSCTIMER_EdgeAlignedPwm
• changed duty-cycle to 20%

Again it works, I saw 24kHz PWM signal with a 20% duty-cycle.

Now I changed duty-cycle to 0% and I expcted to see a static low level signal. However the output signal isn't always low, it shows a very short glitch. It is short, because SCT counts at a frequency of 220MHz and I suspect the glitch duration is a clock tick (4.5ns).

Just to further investigate, I changed the prescaler from 0 (default) to 99 (clock divided by a factor of 100). Now I can see the "glitch" as a 450ns pulse.

So the question is: how to have a true 0% duty-cycle (static low-level signal) with SCT in kSCTIMER_EdgeAlignedPwm mode?

There are some comments in SDK code:

/* Calculate pulse width and period match value:
* For EdgeAlignedPwm, "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period - 1U" results in 100% * dutycyle. For CenterAlignedPwm, , "pulsePeriod = 0" results in 0% dutycyle, "pulsePeriod = period + 2U"
* results in 100% dutycyle.
*/

However it appears this is wrong.

[xiangjun_rong]

Hi, Giuseppe,

You question is that there is one clock high logic when you set the duty cycle as zero, while you expected that the PWM signal is always zero with zero duty cycle.

As you know that the PWM signal is set or cleared by events, the minimum high logic time is 1 tick time, in the case, when the counter reaches up to period-1 value, an event is generated, the PWM signal is set, when the counter reaches up to period value, another event is generated, the PWM signal is cleared. If you want to delete the logic high time, the only way is the first event does not generate. so as a workaround, in edge-alignment mode, you can set the pulsePeriod = period + 2U.

Pls have a try.

BR

XiangJun Rong

[danielholala]

Did this solve your issue?

By the way, a similar observation (glitch at 0% PWM duty cycle) was reported here some years ago.