LPC546XX CTIMER 0 Channel 0

[abdel12312]

Hello NXP community, 

I have a question regarding the configuration of CTIMER0:
Is it possible to have both input capture and match compare active on the same channel?

Based on the block diagram, it appears to be feasible. The datasheet does not explicitly state that each channel is restricted to either input capture or match compare exclusively. I'm asking because all channels are currently in use, and I'm exploring options to track counter register overflows. This could potentially be done using the MR0 register by enabling an interrupt on match—on a channel that is also configured for input capture.

According to section 14.6.3 of the datasheet:

“The 32-bit Timer Counter register is incremented when the prescale counter reaches its terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will count up through the value 0xFFFF_FFFF and then wrap back to 0x0000_0000. This event does not cause an interrupt, but a match register can be used to detect an overflow if needed.”

[Pablo_Ramos]

Hi @abdel12312,

Chapter 14 in the datasheet is the Package Outline. I assume you meant to refer to the User Manual; however, in the User Manual, Chapter 14 is about the Group GPIO Input Interrupt.

The citation you shared comes from Section 17.6.3, "Timer Counter Registers." Is this the section you were referring to?

Also, could you help me confirm if the block diagram you are referring to is in Section 17.4.4 Architecture?

Best Regards,

Pablo

[abdel12312]

Hi @Pablo_Ramos,

Thanks again for looking into this!

I’m referring to the LPC546xx User Manual, specifically:

Section 14.6.3, which notes that Match Register MRx can be used as a software overflow counter by setting it to 0xFFFF_FFFF.
Section 14.4.4, which shows the CTIMER block diagram, indicating that the match and capture subsystems are architecturally independent.
Here’s what I’m trying to confirm:

I currently have CTIMER0 Channel 0 used for input capture, using Capture Register CR0. I’d like to simultaneously use Match Register MR0 (on the same CTIMER and channel) to track the Timer Counter (TC) value — essentially using MR0 as a software overflow threshold.

I do not intend to configure any match output actions (e.g., toggling pins, resetting TC, etc.), and I will not be modifying the EMR (External Match Register). However, I may enable the interrupt on match (via MCR) to detect when TC reaches MR0, purely for software tracking purposes.

From the block diagram, it appears that the match and capture logic are independent, which suggests this should be valid. Could you confirm if this usage is supported, and whether there are any caveats or register interactions I should be aware of when using MR0 in this way alongside CR0?

Here is block diagram iam referring too, also attached UM.

Thanks again!

[Pablo_Ramos]

Hello,

My colleague provided an answer in the following link 

Solved: LPC546XX CTIMER configuration question - NXP Community

I apologize for the delay. 

Regards, 

Pablo