LPC5411x - JTAG boundary scan and SWD / Flexcomm pin descriptions

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LPC5411x - JTAG boundary scan and SWD / Flexcomm pin descriptions

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by bhaack on Tue Apr 05 05:14:57 MST 2016
Hi,
since there is no dedicated forum for the LPC5411x yet, I will post my questions here:

in contrast to previous devices according to datasheet v1.3 LPC5411x uses four separate pins for SWDIO/TMS and SWCLK/TCK. Can I re-connect them to use only one single 10pin-header for SWD-debugging and JTAG boundary scan, or are there technical reasons for spreading these functions to separate pins?

Is /TRST an optional pin for boundary scan, since it it missing on the 10-pin cortex debug connector? Segger uses Pin 9 for /TRST, which is labeled as GNDDetect. Will connecting /TRST to pin 9 interfere with LPCLink2/SWD?

PIO0_23 and PIO0_25 have ambiguous descriptions in table 4 - I assume RTS is in both cases correct for FC1 and FC4?

Regards,
Bjoern
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lpcware
NXP Employee
NXP Employee
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by lpcmunich on Mon Apr 11 07:39:00 MST 2016
Hi Bjoern,
You are right.
The SWDIO/TMS and SWCLK/TCK functions are routed to 4 different pins in case of LPC5410x/LPC5411x.
But I don't see any technical problem in re-connecting them externally to use single 10-pin connector for SWD and JTAG boundary scanning.
Yes, TRST is an optional signal for boundary scanning. But pin-9 is not used by SWD anyway, so you can connect TRST to pin-9.
You seem to be right with regards to pin descriptions of PIO0_23 and PIO0_25 in table-4, these are obvious typos.
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