LPC5411X I2S receive 8 32 bit channels

[Waldemar_MV]

Hi,

we have LPC5411X controller and want to receive data from ADC in not typical format.

ADC have DOUT, CLK, DataReady 1, 2 or 8 lines. Data can be output in these formats:

- 8 x 32 Bit channels on 1 data line in series with 8kSPS data rate.

- Two Data output lines each 4 channels 32 Bit, 8 kSPS
- 8 data lines each one 32 Bit, 8 kSPS

Generally this really fits to the I2S in mode 2, mono 0.
For one line data output format:
Frame can be set to 256 bits FRAMELEN in I2S CFG2 register is for exactly 8 channels by 32 Bit.

Or we cant receive this data like this because for each 32 bit packet we need to have I2S channel ?
Thus need to use two data outputs with 2 Flexcomm interfaces for this as whown in  attached picture ?

[xiangjun_rong]

Hi, Valdemar,

Pls refer to section 23.6.1 Function Summary in UM10914.pdf for LPC5411x, in TDM mode, the I2S only supports two slots, but you required 4 slots, the I2S of LPC5411x does not support 4 slots.

You can consider LPC546xx, it supports at most 8 slots in TDM mode for each I2S module, there are 2 I2S modules.

You can also consider i.mxrt600 family, each I2S module supports at most 8 slots, there are 8 I2S modules.

You can also consider Kinetis or i.mxrt10xx family, it supports 32 slots I suppose.

Hope it can help you

BR

XiangJun Rong

[Waldemar_MV]

Hi XiangJun,

thanks for the reply.
But why :

1)The same user manual have CFG1 register configuration 3:2 PAIRCOUNT 
with option to set 4 channel pairs in (see attachment)

2) Fig.76 show 4 slots on diagram in TDM and DSP modes, mono, with WS pulsed for one SCK time

3) LPC5411X datasheet on 7.19.8 chapter states that
"In the LPC5411x, the I2S function is included in Flexcomm Interface 6 and
Flexcomm Interface 7. Each of these Flexcomm Interfaces implement four I2S channel
pairs"


It seems pretty aligned with
DSP mode packs channel data together in the bit stream and
does not use WS to identify left and right data and
each data transfer between the bus and the FIFO will be a single value with
FIFO configured as 32 bits wide and 8 entries deep.

[xiangjun_rong · Accepted solution]

HI,

I copy the part from UM10912.pdf, which is UM of LPC546xx family.

The I2S of LPC546xx supports 8 slots, it has additional registers such as

P1CFG1 - offset 0xC20;

P2CFG1 - offset 0xC40;
P3CFG1 - offset 0xC60;

P1CFG2 - offset 0xC24;

P2CFG2 - offset 0xC44;

P1CFG2 -offset 0xC64

But the I2S of LPC5411x in UM10914.pdf(UM of LPC5411x) does not have the registers, pls check yourself.

In conclusion, the I2S of LPC5411x only support I2S mode(2 slots) rather than 8 slots(TDM mode).

Hope it can help you

BR

XiangJun Rong

[Waldemar_MV]

Got it, thanks

So,
1) maximum possible, how much bits we can receive in FIFO from one SDA line between two WS pulses with LPC5411X ?

2) Is DSP mode can fill FIFO by packing channels data together in the bit stream until next WS ?

[xiangjun_rong]

Hi,

As you know that there are only two slots, each slot can cover 32bits stream  bits, so the maximum data stream bits between two pulses is 32bits*2=64bits

Hope it can help you

BR

XiangJun Rong