LPC54114 Power consumption at 3.6V

[brulath]

We've got a design using an LPC54114 which we noticed had unexpectedly high deep power-down current of 80 uA, just with the processor and an analog reference voltage attached (2.5V ref, which consumes max 1.5 uA).

Some steps I've followed to debug the issue so far are:

I followed the instructions in the errata re: the ADC excess power consumption and observed no effect whether I left the pins as analog or digital when entering deep power-down.

We were powering VDDA and VREFP from the same 7mA 2.5V reference; when I powered VDDA directly from the same source as VCC at 3.6V (vrefp still 2.5V) the power consumption dropped to 20 uA (from 80).

Following those steps I then tried dropping the input voltage (VCC/VDDA) and observed:

20 uA @ 3.6V

8 uA @ 3.3V

3.5 uA @ 3.0V

2 uA @ 2.5V (vref removed)

Am I configuring something incorrectly or is this expected behaviour? The data sheet only lists 1.62V and 2.0V tests (at 290 nA and 330 nA respectively). This is significantly higher power consumption than the LPC11U68 we replaced, so it's unexpected.

[brulath · Accepted solution]

No fix, they're adding an errata note. Seems we'll need a regulated power rail with a higher reference voltage :smileyhappy:

- B

[miguel_mendoza]

Hi Bruce Andrews,

First of all, thanks for sharing your results, I think that is the expected behavior, because when you are using a voltage reference almost equal to VddA the voltage consumption match with the datasheet.

On the other hand why the consumption increase when you down the reference is something that we can not know because of this voltage is not characterized.

regards,
Miguel

[brulath]

Hi Miguel,

The LPC54114 is designed partially for battery-operated products. If we want to measure the voltage of the battery using the processor's ADC then we require a reference voltage. If we use a reference voltage at an appropriate level (~2V) then the processor will consume a large additional sleep current.

Most of our products are designed to work with single-use LiSOCl2 batteries, which operate from 3.6V (full) to 2.0V (effectively dead). We'd therefore ideally use a 2.0V reference, which would operate down to approximately 2.2V. If we left the reference connected during sleep it would consume ~80 uA, which would compromise the sleep lifetime of the device.

As I noted before, I read the errata regarding the analog circuitry and wasn't able to reproduce the issue it described. Is that issue related to the reference voltage drawing excessive power during sleep or were the analog inputs themselves drawing it?

[brulath]

Following up with NXP via alternate channels. Issue was reproduced at a couple of levels, awaiting resolution.

[miguel_mendoza]

Hi Bruce Andrews,

There are some JS components that if there are not removed an extra leakage current is observed on the top of the specific power consumption for the low power modes.

Please check this application in the link below AN11799 application note, this application notes talk about low power mode of the LPC5411x series and wake-up implementations, also talk and explain an example to enter in the differences low power modes, how to measure the power consumption, and what can cause an extra leakage current.

Tell me if you can solve the problem, and if you still having problems please give more details about what are the exact steps that you are followed to prove it.

regards,
Miguel

[brulath]

Hey Miguel,

I received the LPCXpresso54114 board today and reproduced the issue.

Modify SJ2 to allow an external voltage reference

Provide a voltage reference which is less than 0.3V lower than VddA, where VDD is 3.3V or above.

Place the board into deep power-down mode

Observe the power usage of the processor (measured as instructed) is approx 400 nA

Alter the voltage reference to be more than 0.3V lower than VddA

Note the power usage increases the further below VddA it goes.

With the LPCXpresso54114 board running in 3.3V mode I observed:

Reference at 3.3V: ~400 nA

Reference at 3.2V: ~700 nA

Reference at 3V: ~1 uA

Reference at 2.5V: ~24 uA

The highest figure I was able to reproduce was 78 uA, though that might've been below 2V (which is the specified minimum).

Given these findings we suspect the best we can achieve at 3.6V Vdd is approximately 1.5 uA deep power-down including a 3.0V reference (consuming 350 nA) and RTC.

Is this expected behaviour?

[brulath]

Hi Miguel,

I'm not using the LPCXpresso54114 board, but a design we've created using the 64-pin variant of the LPC54114. I've modified the PMU demo to the equivalent of the following code:

// Just disabling the ADC pins to make sure
static const PINMUX_GRP_T pinmuxing[] = {
 {0, 29, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {0, 30, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {0, 31, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 0, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 1, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 2, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 3, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 4, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 5, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 6, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 7, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
 {1, 8, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_DIGITAL_EN)},
};

int main(void)
{
    SystemCoreClockUpdate();
    Board_Init(); // default, initialises GPIO, led, inputmux/iocon clocks

    // Switch to 12 mHz, as suggested in the application note
    Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_FRO12MHZ);
    LPC_SYSCON->FROCTRL &= ~(SYSCON_FROCTRL_MASK | SYSCON_FROCTRL_HSPDCLK);
    Chip_SYSCON_SetFLASHAccess(SYSCON_FLASH_1CYCLE);
    Chip_POWER_SetVoltage(Chip_Clock_GetMainClockRate());

    // Ensure ADC pins are digital, re: errata
    Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(pinmuxing[0]));

    // <flash some LEDs to create a delay>

    // Deep power-down settings from the periph_pmu example
    NVIC_DisableIRQ(PININT_NVIC_NAME);
    Chip_PININT_DeInit(LPC_PININT);
    Chip_SYSCON_DisableWakeup(SYSCON_STARTER_PINT0);
    Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_INPUTMUX);

    // Enter deep power-down, everything should be disabled
    Chip_POWER_EnterPowerMode(POWER_DEEP_POWER_DOWN, 0);
}

Most of the code above seems to be redundant, but when entering POWER_DEEP_POWER_DOWN with a parameter of 0 I would expect everything except the RTC to be terminated. For some reason we're still seeing a fairly hefty power draw, as I noted above, with just the processor and the 2.5V reference attached.

Physically on the design, using the 64-pin LPC54114, the relevant connected pins are:

Vdd: pins 8, 24, 34, 56 connected directly to 3.6V

Vss: pins 9, 25, 55

VddA: pin 23 connected directly to 3.6V

VrefP_ADC: pin 22 connected to 2.5V reference

VrefN: pin 21 connected to ground

VssA: pin 20 connected to ground

RTC: pins 33, 35, connected to 32.768 kHz

RESETN: pin 64 connected to reset IC and held high

Pins 31, 38: Pulled high

Pins 58, 59, 61: connected to LED

On this test board I'm using, all other components have been disconnected from the main processor. There's no other current-consuming parts other than the voltage reference, which averages 350 nA and maxes at 1.5 uA. With this setup I'd expect an average of around 1 uA sleep, but I'm getting 20 to 80 (depending on whether VddA is connected to 3.6V or 2.5V).

I've reviewed the LPCXpresso54114 schematic and the only difference I've really noted is that the VddA and VrefP are tied to Vcc. We're ordering some of those boards to verify, but in the meantime I'd be interested in any advice you could offer

- B