LPC43xx SDRAM PCB layout / clock trace length

[leecoakley]

I'm designing a board based on the LPC4357 which uses external SDRAM.  I have read a lot about this, including the app notes and posts here, but it never hurts to run the specifics past people.

All the SDRAM lines have been length matched to 30mm +/- 7mm.  The clock line is made longer, 44mm, based on bernhardfink 's advice that this will provide more timing margin.  The question is: is this length matching good enough and is the clock line sufficiently longer than the other signals for reliable operation?  I can easily adjust the clock line to be longer or shorter by a long way.  The others I can match to perhaps +/- 4mm with some effort.

ICs:

The SDRAM is an ISSI is42s32800.  102 MHz operating frequency.

The LPC4357 is the FET256 BGA package.  The clock pin used is CLK0.  The other CLK pins are not used for anything else.

PCB:

This is a six layer board with dedicated ground and power planes. The SDRAM signals are routed on all four signal planes. The signals are routed through a maximum of two vias on their way to the SDRAM, not counting the dogbone escapes from the BGA.

Misc:

Address pins A0/A6/A7/A8 have a 10K pulldown to set the boot mode.  A9 has a 10K pullup for ISP.  The 10K value is an a** pull, please let me know if I should use a different value.

Any suggestions greatly welcomed, as you may save me quite a lot of money. :smileywink:

[ZhangJennie]

HI 

From experience, For SDRAM PCB design, we need make the data lines the same length. and data lines are shorter than the clock line for the timing margin consideration. Data lines and clock line are not the same length.

Besides, I would suggest you read this document, SDRAM interface to LPC18xx/43xx EMC, 
http://www.nxp.com/documents/application_note/AN11508.pdf

This application note describes how to properly interface SDRAM memory to the LPC1800 and LPC4300 External Memory Controller.

Have a nice day,

Jun Zhang

[leecoakley]

Thanks. Actually I had not considered the 4.7K series resistors on the boot/ISP pins so that is one thing to change at least.

The app note recommends length matching within two inches so I'm pretty safe there with +/- 7mm (0.5 inch max difference).

One thing I could use some input on, is how much longer exactly the clock line should be.  At the moment it is 14mm longer than the average length of the other SDRAM lines.  Is that long enough?

[ZhangJennie]

Hi Lee,

I had thought your clock line is 14mil longer than data lines, but just aware it's 14mm longer.

There is no exact value of clock line longer than data lines, but 14mm is too long.

normally  the maximal value is 50mil longer, which is allowed.

consider 100M frequency is not high, 100mil is also ok, but it's better to keep it under 50mil.

Have a nice day,

Jun Zhang

[leecoakley]

Thanks. I will change it to be only 50 mils longer than the longest data line.

What about the matching of the data lines, are they too poorly matched at +/- 7mm?  (up to 500 mils difference)

[ZhangJennie]

Yes，7mm error is too poor. To get the best SDRAM performance, I suggest all the data lines the same length. 

Please try to keep data lines length the same.

[leecoakley]

Okay, thanks.  I will try to match get the data lines perfectly matched.

[bernhardfink]

Hi Lee,

here is some more background information for the EMC in the LPC4300/LPC1800.

The tricky things is:  the reason for delaying the clock signal is, that you want it to appear earlier.

• Internally there is an EMC_CLK signal which is synchronized with the CPU clock. This is used for the control signals and for latching address and data signals going from the EMC to the SDRAM
• In front of the EMC_CLK[3:0] pads there are analog delay circuits which allow to delay the signal by 7 x 0.5ns. So the clock at the external SDRAM devices (EMC_CLK[3:0] is delayed by the physical delay of the PCB track and
  by n x 0.5ns
• Directly at the EMC_CLK pad the clock is taken and is fed back into the EMC as "feedback clock", responsible for latching the RX data coming from the SDRAM. To cover the basic delays in the overall flow for receiving data from the SDRAM, the clock is delayed by half a clock cycle ( respectively appearing earlier by half a clock cycle), realized with an inverter. This solution is simple and in principle it works fine. It has no impact on sending data to the SDRAM.
• But for the receive path the timing got critical at higher frequencies (96MHz and above), also caused by a design problem in the flashless variant LPC4350, where the clock divider for the EMC clock generated an asymmetric clock output. This is less critical on the flash variant LPC4357.
• To get back margin, we added the analog clock delays on top of the 180° delay of the inverter. Sometimes we even added a capacitor on the clock pin to get another 0.5ns and also longer clock lines helped a little bit. This takes away some of the margin on the timing for writing to the SDRAM, but it works. For RX from the SDRAM these measures are crucial. Otherwise the timing of the data signals from the SDRAM and the decisive edge of the feedback clock do not match
• In the end the recommendation for the PCB designers was:
  • Make the data/address/control lines reasonably short and try to match them in length
  • Make the clock signal track at least not shorter than the other tracks
  • Foresee a footprint for a small capacitor at the clock signal, in case an additional delay is needed
• Software settings are another step, changes and adjustments during development and final testing don't hurt that much. Finally the system must be stress tested under frequency and temperature conditions using individual settings.
  • Test cold and hot, go beyond the limits to see how much margin you have
  • Clock the EMC faster than for normal operation

In specific SDRAM stress tests I used the following parameters:

#if (defined(BOARD_HITEX_EVA_1850) || defined(BOARD_HITEX_EVA_4350))
  #if (defined CLOCK_DIVIDER)
     // Hitex board with 180/90 MHz, ISSI SDRAM or Winbond SDRAM
    #define CLK0_DELAY         7
    #define CLK1_DELAY         7
    #define CLK2_DELAY         7
    #define CLK3_DELAY         7
  #else 
        // Hitex board with 120/120MHz, ISSI SDRAM or Winbond SDRAM
    #define CLK0_DELAY         5
    #define CLK1_DELAY         5    
    #define CLK2_DELAY         5
    #define CLK3_DELAY         5  
    #endif
#endif

#if ((defined(BOARD_KEIL_MCB_1857) || defined(BOARD_KEIL_MCB_4357)))
  #if (defined CLOCK_DIVIDER)
        // Keil board with 180/90 MHz, Micron SDRAM 32-bit
    #define CLK0_DELAY         7
    #define CLK1_DELAY         7
    #define CLK2_DELAY         7
    #define CLK3_DELAY         7
  #else
    // Keil board with 120/120MHz, Micron SDRAM 32-bit
    #define CLK0_DELAY         5
    #define CLK1_DELAY         5    
    #define CLK2_DELAY         5
    #define CLK3_DELAY         5  
    #endif
#endif

Providing exact value for this and that is not possible, it always depends on the operating conditions and the SDRAM type when the interface timing runs out of margin. Special care must be taken when replacing the SDRAM during lifetime of the end product, the new SDRAM could perform worse than the original one.

I hope this helps clarifying the topic,

Bernhard.

[leecoakley]

Thanks very much for the in-depth explanation Bernhard, I understand the reasoning much better now.

I'll take the advice into account as much as possible. Wish me luck. :smileyhappy:

[leecoakley]

My line of thinking is that I'm being too conservative with the CLK length.  The clock delay register adds 500ps per step.  Meanwhile my clock line is 14mm longer than the others.  The signal propogation rate across the PCB lines is something like 1 millimetre per 6 picoseconds making the difference only 85ps.  Seems like small potatoes compared to what can be achieved with the delay reg.

That also puts the length matching in perspective, now that I think of it...