LPC43xx ADC multiple channels with DMA

[mtenw]

I am trying to sample multiple channels from both ADC0 and ADC1 at the same time using timer match signal. Specifically, I am using LPC4370. Thanks to Rocky's previous post at http://community.nxp.com/message/829205, I have a better idea of doing this. However, instead of using interrupts, I need to use DMA in order to sample multiple channels at higher rates, for example, 8 channels at ADC0 each at 50kHz. Some questions occur to me when I think of this approach:

1. When a timer match signal occurs, is channel 0 sampled first, then after 11 ADC clock cycles, channel 1 is sampled, ... and so on. Can anybody confirm this?

2. I want to keep samples from both ADC0 and ADC1 in memory in the order of the time that is sampled. Does it require 2 DMA channels? Can it be done using 1 DMA channel?  What is the best way to do it?

Any help is appreciated. Thank you so much.

[jeremyzhou]

Hi mtenw,

1. When a timer match signal occurs, is channel 0 sampled first, then after 11 ADC clock cycles, channel 1 is sampled, ... and so on. Can anybody confirm this?

Yes, however the important drawback of the approach is the destination address variation, as the result of a hard-ware triggered conversion is stored in the individual channel data registers DR0 to DR7 and in software-controlled mode, only one of these bits should be 1.

2. I want to keep samples from both ADC0 and ADC1 in memory in the order of the time that is sampled. Does it require 2 DMA channels? Can it be done using 1 DMA channel?  What is the best way to do it?

Definitely, it should need two DMA channels.

Hope this is clear.
Have a great day,
Ping

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[mtenw]

Hi Ping,

Thank you for the reply. It is very helpful.

Could you please elaborate your answer for Question 1?

Specifically about the statement "only one of these bits should be 1", do you mean one of the bits in DR0 to DR7?

Also, could you please explain your statement about "important drawback of this approach"?

Thank you for the help!

[jeremyzhou]

Hi mtenw,

1. When a timer match signal occurs, is channel 0 sampled first, then after 11 ADC clock cycles, channel 1 is sampled, ... and so on. Can anybody confirm this?

When ADC is configured to enable hardware-triggered mode, any value containing 1 to 8 ones is allowed versus only one of these bits should be 1( Seeing Fig 1).

The result of a hard-ware triggered conversion is stored in the individual channel data registers DR0 to DR7. The global data register does not yield valid readings of a hardware-triggered conversion.

So it's a little complicate to setup DMA to transfer the data from the different source address when per ADC DMA request generates and the approach is not desirable.

Fig 1

Hope this is clear
Have a great day,

Ping

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[mtenw]

Hi Ping,

Thank you for the quick response. That clarifies my questions.

But this brings back my original Question 2. If setting up different source addresses (DR0 to DR7) for DMA is not a desirable approach. What would you suggest to implement Question 2?

Thank you for the help!

[jeremyzhou · Accepted solution]

Hi mtenw,

Thanks for your reply.

If setting up different source addresses (DR0 to DR7) for DMA is not a desirable approach. What would you suggest to implement Question 2?

In the Rocky's reply, it had pointed out the most important question: sample 2 analog source simultaneously. Now you want to integrate the DMA engine to achieve the higher sampling rate and definitely, the DMA engine is the better choice than fetch the sample data in the IRQ mode.

To implement it, the hardware source for the ADC is identical with the Rocky's proposal, to integrate the DMA engine, for instance, ADC0 use the DMA channel 0 and set the ADC0 as the DMA source request peripheral in the DMA channel configuration register, ADC1 can use another DMA channel except the channel 0 and set the ADC1 as the DMA source request peripheral in the DMA channel configuration register.

You can learn the more information about the DMA flow control in the section 21.8.2 Flow control.

Hope this is clear.
Have a great day,
Ping

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[mtenw]

I wonder if NXP tech support or anyone in the forum could provide suggestions on this matter. Please help. Thank you.