LPC43xx 200MHz issue

[samkaos]

I am running a LPC43xx @ 200MHz

Occasionally (not very often), the PLL does not lock during power up and code stops when switching over to the PLL clock.

I have tried stepping the clock to 100MHz then to 200MHz as per everything I can find, but it doesn't work.

External 11.0592MHz Xtal.

-Sam

[samkaos]

Thanks for the reply!

I have seen optimisers remove loops, I will have a look at that.

Tested on 2 completely different PCBs I have designed (one is 2 layer, one is 6 layer).

The CPU stops processing completly (crash)

I thought about that.  There is oodles of capacitors around the CPU and the power supply can supply amps (again 2 different supplies used.) I was thinking of adding an external BOD (supervisor) in case the power supply is slow rising.

I will try to do some experiments this week.

[bernhardfink]

Hi Sam,

With "weak power supply" I did not mean that it is not able to deliver enough amps from somewhere in the backbone, it's more the local dynamic performance which generates problems. The LQFP package for example has pins and bonding wires, then there is the PCB with it's parasitic elements. All this will sum up and can lead to transient spikes on the power supply when the system load changes quickly. These are effects which influence the internal regulator, it can cause power drops on the core supply voltage and therefore a crash. You will not see a power drop at the outside with an oscilloscope, you might only see some transients, but you can't see the consequences.

The 256BGA package has a lot of power and ground pins and by design very little parasitics. The LQFP package has only a few ground pins, if you did not make the connection to these pins with a ground plane but with wires then you most likely run into problems. A 2-layer PCB is more or less impossible, except if heavily focus on perfect power connections.

In software you could try to relax things by removing loads from the system during system clock changes. So if you switch the PLL to higher frequencies, you should connect as many blocks as possible to another time domain (for example the 12MHz domain), set up the PLL and then re-connect the blocks to the PLL output.

regards,

Bernhard.

[samkaos]

I have tried using PSEL of PLL1 to change divider, I have tried using IDIVA / 2, then changing IDIVA to /1 after a delay and I have tried IDIVA / 2, then switching to PLL1 direct as below:-

// Setup PLL1 (CPU ETC)
LPC_CGU->XTAL_OSC_CTRL = 1 | (1<<1);
LPC_CGU->XTAL_OSC_CTRL = (1<<1); // External OSC, <15MHz

localTemp32 = 0;
while(localTemp32 < 50000) // Wait for Xtal to stabilize
{
LPC_WWDT->FEED = 0xAA;
LPC_WWDT->FEED = 0x55; // Watchdog
localTemp32++;
}

// LPC_CGU->PLL1_CTRL = 1|(1<<6)|(17<<16)|(6<<24);//|(1<<11); // 199.0656MHz
LPC_CGU->PLL1_CTRL = (1<<6)|(17<<16)|(6<<24);//|(1<<11); // 199.0656MHz
localTemp32 = 0;
while((LPC_CGU->PLL1_STAT & 1) == 0x0 && localTemp32 < 100000) // Wait for PLL to lock
{
LPC_WWDT->FEED = 0xAA;
LPC_WWDT->FEED = 0x55; // Watchdog
// localTemp32++;
}

LPC_CGU->IDIVA_CTRL = (1<<2)|(9<<24);//|(1<<11); // IDIVA = PLL1 / 2 (99.5328MHz)
LPC_WWDT->FEED = 0xAA;
LPC_WWDT->FEED = 0x55; // Watchdog
LPC_CGU->BASE_M4_CLK = (0x0C<<24);//|(1<<11); // Set to IDIVA (99.5328MHz)
LPC_CGU->BASE_PERIPH_CLK = (0x0C<<24);//|(1<<11); // Set to IDIVA (99.5328MHz)
LPC_CGU->BASE_APB1_CLK = (0x0C<<24);//|(1<<11); // Set to IDIVA (99.5328MHz) // CAN1, I2C0, PWM
LPC_CGU->BASE_APB3_CLK = (0x0C<<24);//|(1<<11); // Set to IDIVA (99.5328MHz) // CAN0, I2C1, DAC, ADC
LPC_CGU->BASE_SPIFI_CLK = (0x0C<<24);//|(1<<11); // Set to IDIVA (99.5328MHz)

localTemp32 = 0;
while(localTemp32 < 50000) // Wait for CPU
{
LPC_WWDT->FEED = 0xAA;
LPC_WWDT->FEED = 0x55; // Watchdog
localTemp32++;
}

LPC_CGU->BASE_M4_CLK = (9<<24);//|(1<<11); // Set to PLL1 (199MHz)
LPC_CGU->BASE_PERIPH_CLK = (9<<24);//|(1<<11); // Set to PLL1 (199MHz)
LPC_CGU->BASE_APB1_CLK = (9<<24);//|(1<<11); // Set to PLL1 (199MHz) // CAN1, I2C0, PWM
LPC_CGU->BASE_APB3_CLK = (9<<24);//|(1<<11); // Set to PLL1 (199MHz) // CAN0, I2C1, DAC, ADC
LPC_CGU->BASE_SPIFI_CLK = (9<<24);//|(1<<11); // Set to PLL1 (199MHz)

[kerryzhou]

Hi Sam,

   In the code, before you do the PLL clock configuration, you can add some delay, just to wait the external osc stable.

  Then try it again.

  As I know, after power on, the external crystal oscillate stability need time, if the external crystal is still not stable, then you configure the PLL, it may can't lock.

   So, please try it on side.

   If you still have question about it, please kindly let me know.

Have a great day,
Kerry

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[samkaos]

I do have a crystal stabilization delay:-

localTemp32 = 0;
while(localTemp32 < 50000) // Wait for Xtal to stabilize
{
LPC_WWDT->FEED = 0xAA;
LPC_WWDT->FEED = 0x55; // Watchdog
localTemp32++;
}

-Sam

[bernhardfink]

Hi Sam,

few questions/notes from my side:

• make sure that the delay loop wasn't optimzed away from the compile somehow, just look with the debugger into the assembler code to see what the compiler made out of it.
• as the PLL setup works most of the time, your're somewhere at the edge with the setup. This might be software or hardware setup. Software is easy to change, hardware not. Do you perform the test on your own board or on an evaluation board from NXP or a 3rd party?
• What happens when you have the failure? You write "code stops when switching over to the PLL clock". Does this mean there is a crash, where you completely lose the debugger connection or does the code go into an exception error?
• A weak power supply design could be the reason for problems when switching to a higher performance mode, for example from 100MHz to 200MHz. Which package of the LPC43xx do you use, BGA or LQFP?

Regards,

Bernhard.