LPC4370 ADCHS / HSADC DMA write request

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LPC4370 ADCHS / HSADC DMA write request

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SynBilly
Contributor III

Hi everyone,

I'm trying to get ADCHS / HSADC up and running using an automated update of the descriptor tables. The user's manual section 48.7.3 states "when swapping tables a DMA request can be raised to enable the DMA to load a new table [..]". In fact, using the "SWAP tables" bits in the descriptor table, no DMA write request is fired. However, setting the DMA_REQ_WR bit fires a request and the descriptor table is updated.

How can an automatic DMA based reload of the descriptor tables be archieved?

Cheers!

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jeremyzhou
NXP Employee
NXP Employee

Hi Sabine Pfeifer,

Thank you for your interest in NXP Semiconductor products and 
for the opportunity to serve you.
The BRANCH bits is used to configure the descriptor processing order, not to raise the DMA request.
So I was wondering if you can upload the demo code and introduce it in details, as it will help me to work it out.
Have a great day,

TIC

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SynBilly
Contributor III

Hi TIC,

thanks for your reply! The question we asked can be reduced to "Is it possible to fire a DMA write request from within a descriptor?". The quoted text from user's manual section 48.7.3 suggests that it would be possible.

This information is essential for an aquisition sequence we want to use. Sorry, but we don't have any example code ready to post here, hence the basic question.

Cheers!

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jeremyzhou
NXP Employee
NXP Employee

Hi Sabine Pfeifer,

Thanks for your reply.

1) Is it possible to fire a DMA write request from within a descriptor?

-- Yes, it's
Have a great day,
TIC

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SynBilly
Contributor III

Hi TIC!

Thanks for your reply.

-- Yes, it's

Nice! How? Which bit in a ADCHS descriptor does the trick?

Cheers!

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jeremyzhou
NXP Employee
NXP Employee

Hi Sabine Pfeifer,

Thanks for your reply.

Please following the UM statement to set the BRANCH bit=0b10.

Have a great day,
TIC

 

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