LPC4367's M0Sub access to used SSP0 peripheral

[gauravmore]

Hi,

I am using LPC4367 controller with On chip flash and RAM and in Tri core mode. I want M0Sub core to use SSP0 bus to read the data from External SPI based ADC.

Is it Possible to use SSP0 through M0SUB core? since we are SPIFI  for QSPI and no SPI line is available for us to use.

Please confirm since were are planning to interface ADC over SSP and access it through M0Sub core.

It will be very helpful..

Thanks

Gaurav More

[Alexis_A]

Hello @gauravmore,

As it mention in the User Manual:

The other ARM Cortex-M0 core (M0SUB) - if available - is typically used to control the SGPIO and SPI peripherals. This core is connected through a bridge to the main Cortex-M4 processor.

The SPI interface that is mentioned is not the SSP0, is the one mentioned in the chapter 43.

Best Regards,

Alexis Andalon

[gauravmore]

Hi Alexis Andalon,

Thanks for the reply,

I am aware regarding the SPI interface but currently we are using SPIFI lines to access QSPI flash in our application and so we are not able to get the SPI lines. We are planning to use this M0sub core to use SSP0 to get the external data for the peripheral. 

So even if it is not having access but if we use it then will it be possible considering some sort of latency in the operation of SPI lines? since it is connected through the bridge to the main cortex M4 controller.

Thanks

Gaurav More

[Alexis_A]

Hello @gauravmore,

The best way to do this would be to use the GPDMA to move the data from the SSP0 to a local M0SUB SRAM.

However, you should be able to access the SSP0 since the interrupt is listed in the M0Sub IRQ list at the table 9.6.3 but the access latency would be more than accessing directly from the M4 core.

Best Regards,
Alexis Andalon

[gauravmore]

Hi Alexis,

Thanks for the reply, 

I checked the access of SSP0 through M0Sub Core, I am able to read the device ID of the SPIFI Flash (W25Q128JV) interfaced in the Evaluation board OEM13088 over SSP0 as well. I used the polling mode till now. So if it is working with the polling mode then it should work in interrupt mode as well,

Regarding the latency, that need to be verified since we will be using SSP0 for triggering the ADC and reading the sample from it.

Also will explore the GDPDMA feature to use it while reading the samples from ADC.

Test code for SSP with Device ID reading and the multicore project  also attached. request you to please check if any project setting need to be modified or not.

BR,

Gaurav More