LPC4327 SPI bit shift issue when speed up to higher bit rate

[AndreChuang]

Hi NXP sir,

We met a SPI bit shift issue and would appreciate any tips and help.

We use LPC4327, SPI Master 8bits mode 3 (use SSP1 + DMA).
(1) When we set SPI bit rate up to 20.4MHz. The bit shift issue is occurrence. For example, MISO received 0xC6, 11000110'b by register. But real value is 0x8D, 10001101'b by oscilloscope & logical analyzer.
(2) When we set SPI bit rate up to 20.3MHz (or smaller). The bit shift issue not happen.
(3) We observed SCR change from 5 to 4 between (1) and (2).
SSP1's SCR (in address 0x400C 5000) is 5 -> 4
SSP1's CPSDVSR (in address 0x400C 5010) is 2
Our clock source use 204MHz.
(4) We study the product data sheet "LPC435x/3x/2x/1x Rev. 5.4 - 10 January 2020" too. Chapter 7.19.3.1 and 7.19.4.1 have maximum SSP or SPI speed 25 Mbit/s. So we think 20.4 MHz should be successfully.

Thanks.

AndreChuang

[xiangjun_rong]

Hi,

As Frank said, maybe this is signal integrity issue, pls try to use 4 layers PCB, the middle layers are GND and VDD, it will improve the quality of high frequency signals.

BR

XiangJun Rong

[AndreChuang]

Hi XiangJun,

  I will try to check NXP product data sheet. as below reply.

  Thank you~

BRs,

  Andre

[frank_m]

> Chapter 7.19.3.1 and 7.19.4.1 have maximum SSP or SPI speed 25 Mbit/s. So we think 20.4 MHz should be successfully.

This is only one part of the equation.
Your PCB layout & design (and thus the characteristic impedance) is equally important.
Do you have series resistors in the signal lines ?
Is the trace layout fit for at least 10 x the signal frequency ?

Try a clock frequency of about 1MHz. If there is no bit shift issue, it is signal quality and reflections, caused by the layout.

[AndreChuang]

Hi Frank,

  Thanks for your reply.

  (1) Series resistors in the signal lines ? No.

  (2) Try a clock frequency of about 1MHz. => No bit shift issue.

  (3) We have tried reduce the length of the signal line(CLK, MISO. MOSI). The bit shift issue has improved, but it still occur. (The phenomenon from "always" to "often")

  (4) Now, I try to check again about NXP SSP dynamic characteristics timing Spec (SSP pins in SPI master mode) on oscilloscope.
    Note: Reference "LPC435x/3x/2x/1x Rev. 5.4 - 10 January 2020 Product data sheet" Chapter 11.12~14

  (5) Is the trace layout fit for at least 10 x the signal frequency ? => How to judgement this spec.

Thanks a lot~

BRs,

    Andre

[frank_m · Accepted solution]

I think this is a clear indication that this is a signal deterioration issue.

I think you are familiar with Fourier analysis, which allows you to specify a signal as a superposition of a fundamental frequency and it's harmonics. For a rectangular wave with 20MHz, you quickly get beyond 200MHz of bandwidth requirements to get a decent signal form.
PCB layout and ground layers become important. And series resistors help to attenuate reflections and have an acceptable line impedance.
Even measuring with a scope gets difficult at this frequencies, the probe will definitely influence the signal, and improper probe impedance might totally mess it up.

Though I am no hardware guy, I must add.

A pragmatic solution would be to lower the SPI clock until you get stable & correct results. I would test this at the maximum allowable ambient temperature for your device, since heat tends to worsen such effects.

[AndreChuang]

Hi Frank,

Thanks for your quick reply.
I tried to check MISO setup time is met SPEC (Measure around 15 ns on OSC, the specification is > 12.2 ns). and we checked the loopback mode is normal too. So, we will review layout about SPI.
Your suggestion is pretty useful.
Thanks for your help & analysis.

BRs,

  Andre