Hi,
Q1. The datasheet seems to indicate that MAM is disabled by default. But when the software runs after a reset, the CPU is indicating it is set to 2 (fully enabled). Does this mean that some initial batches of LPC2368 has it 0 (off), and newer batches has set it to 2 (fully enabled)?
>>>>>If the MAMTIM register is not the same with the default 0x07, I suppose it must be modified by the code somewhere.
Q2. We actually have another board which has the Watchdog triggered intermittently even without heat. Does this mean that there's an internal fault in the MAM of the CPU? Or is there a fault in the peripherals connected to the CPU?
>>>>Yes, the MAMTIM value must match with your system clock frequency.
7.9 MAM usage notes
When changing MAM timing, the MAM must first be turned off by writing a zero to
MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turned
on again by writing a value (1 or 2) corresponding to the desired operating mode to
MAMCR.
For a system clock slower than 20 MHz, MAMTIM can be 001. For a system clock
between 20 MHz and 40 MHz, flash access time is suggested to be 2 CCLKs, while in
systems with a system clock faster than 40 MHz, 3 CCLKs are proposed. For system
clocks of 60 MHz and above, 4CCLK’s are needed.
Q3. Do you have a rough idea what is the performance penalty with MAM disabled? Will it be twice slower than before?
>>>>>If the MAM is disabled, I think the default 7 clcok cycles delay will be enabled. Regarding the performance penalty, I think reading flash will use 7 clock cycles delay, when the instruction is in the instruction pipeline, it will be fast.
Hope it can help you
BR
XiangJun rong