LPC2103 PLL setup with Keil µVision and Peripheral Clock, what is XCLKDIV?

[lpcware]

Content originally posted in LPCWare by Han_Mono on Mon Mar 07 05:54:03 MST 2016
Hello everyone,


I'm currently working on revising an old project which was handed over to me with a LPC2103 where I need to port all communication from IIC to Uart.
Sounds easy and it should be, but I'm running into clock problems.

Setup:

Xtal: 16,9344MHz
PLL multiplier: 3
APDIV: 4 (called VPBDIV in microvision)

Therefore the CPU should clock at 50,7MHz, the Peripheral/uart clock should run at 12,7MHz and I decided to run Uart at 38400 Baud.

But in the startup.s/Keil's config wizard there's a something called XCLKDIV, which I assume is the external oscilator input divider which was also set to 4.
No my real problem is that I do not understand or find what XCLKDIV really is and what it does, because to me it seems it doesnt act as a divider but as a multiplier.

Example: I have Uart0 configured to run at 38400 Baud but it actually runs at 156K, so 4 times the Baud I set. Setting XCLKDIV to 1 (== CLK) it runs at 38400 Baud but some other peripherals stop working correctly.

Could someone please tell me what that XCKDIV is?

best
Han

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by Han_Mono on Wed Mar 09 02:57:07 MST 2016
Thx, for your reply.

I decided to live with the settings in the Keil file, and adjusted the Uart config accordingly, despite the fact that it's not running at the calculated baudrate...
it really bugs me not to understand this though.

[lpcware]

Content originally posted in LPCWare by dmitryf on Mon Mar 07 20:24:59 MST 2016

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Quote: Han_Mono
Hello everyone,


I'm currently working on revising an old project which was handed over to me with a LPC2103 where I need to port all communication from IIC to Uart.
Sounds easy and it should be, but I'm running into clock problems.

Setup:

Xtal: 16,9344MHz
PLL multiplier: 3
APDIV: 4 (called VPBDIV in microvision)

Could someone please tell me what that XCKDIV is?

best
Han

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It is a mistake in Keil's startup file. It modify APBDIV divider register bits 5:4 which are should be set to 0 according 2103's manual.

; VPBDIV definitions
VPBDIV          EQU     0xE01FC100      ; VPBDIV Address

;// <e> VPBDIV Setup
;// <i> Peripheral Bus Clock Rate
;//   <o1.0..1>   VPBDIV: VPB Clock
;//               <0=> VPB Clock = CPU Clock / 4
;//               <1=> VPB Clock = CPU Clock
;//               <2=> VPB Clock = CPU Clock / 2
;//   <o1.4..5>   XCLKDIV: XCLK Pin
;//               <0=> XCLK Pin = CPU Clock / 4
;//               <1=> XCLK Pin = CPU Clock
;//               <2=> XCLK Pin = CPU Clock / 2
;// </e>
VPBDIV_SETUP    EQU     1
VPBDIV_Val      EQU     0x00000002