LPC18xx SDMMC, ACMD51 or CMD6 Reply

[romanleonov]

Hi!

I try to get SD Configuration register answer (ACMD51) or SWITCH CONFIG (CMD6) reply on LPC18xx (LPC1822, LPC1837 or LPC43xx, all the same).

Unfortunatelly, I have a problem here, because 512 bytes of data (READ/WRITE SINGLE BLOCK) works well for me.

But when I try to get less data than 512 bytes "Data Transfer Over" Interrupt not follow then. 

So, I set BLKSIZ, FIFOTH and BYTCNT registers to get 8 bytes (64 bits) reply for SD configuration register. 

And I can see reply throw analyzer, but there is no IRQ then in my software. So I can't get reply data from FIFO.

Here my settings:

LPC_SDMMC->BLKSIZ = 1; // 1 byte for block

/* RX_WMark = 0, TX_WMark = 15 (doesn't matter in rx mode i think) and MSize = 1 transfer */

LPC_SDMMC->FIFOTH = (15 << SDMMC_FIFOTH_TX_WMARK_Pos) | 
(0 << SDMMC_FIFOTH_RX_WMARK_Pos) | 
SDMMC_FIFOTH_DMA_MTS_1;

/* then i configure sdmmc descriptor to receive 8 bytes of data. One chain descriptor */

LPC_SDMMC->BYTCNT = 8; // 8 bytes for recieption

/* then i send ACMD51 command */

But there is no IRQ.

Does someone tryed to get reply for ACMD51 or CMD6 sdmmc command on LPC18xx?

Maybe without DMA, just read data straight from FIFO.

[romanleonov]

Finally, I've solved the problem.

1) Command ACMD51 amd CMD6 are commands with data. So wee need to set DATA_EXPECTED bit in CMD register. Otherwise DMA wouldn't try to receive any data and we haven't IRQ DU, as I wrote before. That's why.

2) After settings this bit, we can check RINTSTS register to NIS flag. 

3) BYTSIZ and FIFOTH doesn't influence. So it could be the same as to READ SINGLE BLOCK command.

Here is my list of actions:

/* BLKSIZ */

LPC_SDMMC->BLKSIZ = sd_sector_size; // 512, no problem it's OK

/* setup descriptor for data reception */

sdmmc.descr[0].buf1 = data; // some pointer, 32 aligned
sdmmc.descr[0].buf2 = NULL; // one chain descriptor
/* set size */
sdmmc.descr[0].size = (size << SDMMC_DESC1_BS1_Pos) & SDMMC_DESC1_BS1_Msk; // size - 8 bytes for ACMD51 and 64 bytes for CMD6.

/* first descriptor and last, own by dma */
sdmmc.descr[0].ctl = SDMMC_DESC0_FS_Msk | SDMMC_DESC0_CH_Msk | SDMMC_DESC0_OWN_Msk | SDMMC_DESC0_LD_Msk;

/* setup size */
LPC_SDMMC->BYTCNT = size;

/* send cmd */

sdmmc_cmd(SDMMC_CMD_SWITCH_FUNC, (CF_MODE_CHECK << CF_MODE_OFFS) | 0xFFFFFF, &resp, SDMMC_NO_RESPONSE); // my implementation with cmd reg fill and send cmd to card, verify answer and so on ...

/* wait DMA flag */

while((LPC_SDMMC->IDSTS & SDMMC_IDSTS_NIS_Msk) == 0)); // possible improve with timeout, but OK

/* now we can extract or parse data from data buffer */

...

/* here is my example of switch function reply */

max current: 50 mA
group 6: 8001
group 5: 8001
group 4: 8001
group 3: 8001
group 2: 8001
group 1: 8003
group 6 mode: 0
group 5 mode: 0
group 4 mode: 0
group 3 mode: 0
group 2 mode: 0
group 1 mode: 1
ds version: 0

For more information I used Physical Layer SD Specification Version 3.00 from SD Group. CMD6 reply data is described "4.3.10.4 Switch Function Statuson",  page 52.

Hope, someone find this topic helpfull or interesting at least. 

[romanleonov]

I discovered that I got DU interrupt if I had disabled OWN bit in DMA Descriptor during READ SINGLE BLOCK COMMAND.

But when I do the same with 64 bytes read of CMD6 reply interrupt DU does not occure.

Seems that DMA doesn't try to initiate receiption at all.

Research in process ...

[romanleonov]

I checked registers descripton again and it seems that I do not need BLKSIZ and BYTCNT at all.

Because reading 8 bytes - it is not a block tranfer.

So I guess that I need antoher way how to tell MCI amount of bytes to receive.

Antoher question is that in user manual DATA register is described (>= @0x40004100), but there is no such address in CMSIS library :smileysad: