LPC1857: Is it possible to configure AHB bus masters priorities ?

[samyfantar]

Hello,

In the context of a project for Viveris Technologies, I'm developping an application for a LPC1857 microcontroller that intends to display a user interface on a 800*480 LCD TFT screen.

I'm facing serious problem with framebuffer and screen synchronization. The UI displayed is shaking horizontally while the application continuously runs.

Framebuffer is located on an external 8Mo SDRAM (other datas accessed by the application are located on this external SDRAM). However, if I halt the CPU in debug session, or if the application is doing nothing (empty while loop) after filling the framebuffer, the screen stabilizes itself.

The LCD controller configuration and LCD timings parameters are fine.

My suspicion is about an AHB arbitration concurrency between the CPU (application accessing datas in SDRAM) and the LCD controller (LCD DMA FIFOs trying to get pixel datas in the framebuffer).

In the LPC18xx User Manual Rev 2.8 (p.29), it appears that " When two or more bus masters try to access the same slave, a round robin arbitration scheme is used; each master takes turns accessing the slave in circular order ". However, I can see on p.504 that EMC (the slave connected to SDRAM) has his own priority connection as follows :

1. LCD controller

2. M3 S-bus

3. M3 I/D-bus

4. Other bus masters

But that's not enough apparently. Moreover, I don't find something about changing AHB bus master priorities (CPU and LCD controller) in the User Manual.

My question is how can I increase the priority of the LCD controller over the CPU or what could be the other source of this horizontal unsynchronization ?

Thank you very much for your replies.

All the best,

Samy.

[Hui_Ma]

Hi

The LCD controller is one of the Bus master in LPC1857 and has the highest priority to access EMC port.

If there are bus masters with same priority, LPC1857 uses round Robin bus arbitration method. In this controller we can not prioritize bus master’s access to a slave port.

Please see below the fix priority level from high to low to access EMC port.

1.    LCD controller ->Highest

2.    M3 S-bus

3.    M3 I/D-bus

4.    Other bus masters ->Lowest

Therefore, if LCD controller and other bus request simultaneous access, LCD controller will be granted access. Although the LCD controller has highest priority, however it can still be stalled if another lower priority access has started that has a long burst length .

To avoid starvation, short burst size should be used to tune overall performance.For example if you are using GPDMA, an another bus master on this multilayer bus to access EMC port, I would like to have a smaller bust size to avoid any starvation.

To avoid data underflow the LCD controller also has a large FIFO (16x64 bit). So the LCD FIFO needs to buffer enough data to keep the LCD refreshed - smoothly - even when the system is under load. In some cases, system events can occur that cause the LCD FIFO fill to be delayed.

For example, the CPU might be doing a burst read from SDRAM (memcpy, or maybe an LDM operation with a stack pop), but this may get stalled due to a SDRAM refresh cycle. If multiple stalls like this happen, it can cause delays to the LCD refresh cycle and the LCD FIFO will eventually underflow and you may get a display glitch/shaking. In general if you are using 16 bits SDRAM data interface with multiple bus masters, there are more chances of shaking than with 32 bit SDRAM data interface. Please find below link which has bandwidth calculator

http://www.lpcware.com/content/nxpfile/lcd-bandwidth-calculator-lpc18xx-and-lpc43xx

This calculator is a good tool to check loading on the EMC bus.

Wish it helps.

Have a great day,
Ma Hui
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