Hi Nico Aprile,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
Please follow the below guide to implement it.
Have a great day,
TIC
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Hi
Thanks for your reply.
1) The table 134 of the attached file shows the possible configuration, can you tell me what I have to choose?
-- Please check the Fig 1.
Fig 1
2) From the hardware point of view, is there any modifications to do?
-- No, just like you connect a 32-bit SDRAM(as the Fig2 shows).
Fig 2
Hope this is clear.
Have a great day,
TIC
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Hi, jeremyzhou,
old SDRAM (128 Mb) is the IS42S32400F model (http://www.issi.com/WW/pdf/42-45S32400F.pdf)
new SDRAM (512 Mb) is the IS42R32160F model (http://www.issi.com/WW/pdf/42-45R-S-32160F.pdf)
Below the new SDRAM connections
Attached you can find my SDRAM configuration and test code
Many thanks
Regards
Thanks for your reply.
1. It seems a bit weird that the SDRAM would work well after setting the addressing map as the Fig1 illustrates, it is definitely inconsistent with its datasheet. So I have no idea now.
Fig 1
2. I've attached an SDRAM demo, please use it as the template demo code and run it for testing.
Have a great day,
TIC
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Hi jeremyzhou,
Now the SDRAM seems to work fine. I used the routines you sent me but I had to change something. I had to force the "add_mapped_p1" value. The routine modified is the following:
EMC_FUNC_CODE EMC_DynMemConfigAM(uint32_t index,
uint8_t addr_bus_width,
uint8_t addr_map,
uint8_t data_bus_width,
uint16_t chip_size)
{
const int chip_max_size = 512; // 512Mb
uint8_t data_bus_max_size = 0;
uint32_t add_mapped_p1 = 0x00, add_mapped_p2 = 0x00, add_mapped_p3 = 0x00;
uint32_t tmp = 16, i = 0, j = 0;
/* Get part 3 of address map */
switch(addr_bus_width)
{
case 16:
add_mapped_p3 = 0;
data_bus_max_size = 16;
break;
case 32:
add_mapped_p3 = 1;
data_bus_max_size = 32;
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
/* Get part 2 of address map */
add_mapped_p2 = EMC_DYNAMIC_CFG_ADD_MAP_P2(addr_map);
/* Get part 1 of address map */
if(chip_size == 16)
{
if (data_bus_width == 8) add_mapped_p1 = 0;
else if(data_bus_width == 16) add_mapped_p1 = 1;
else return EMC_FUNC_INVALID_PARAM;
}
else
{
while(1)
{
i++;
tmp = 16*(0x01 << (i+1));
if(tmp == chip_size)
{
for(j = 0; (8<<j)<=data_bus_max_size;j++)
{
if((8<<j) == data_bus_width) break;
}
if( (8<<j) > data_bus_max_size) return EMC_FUNC_INVALID_PARAM;
add_mapped_p1 = (i<<2) + j;
break;
}
if(tmp >= chip_max_size)
{
return EMC_FUNC_INVALID_PARAM;
}
}
}
//SDRAM ISSI da 512 Mbit model IS42S32160F_7TLI 16Mx32 (4M x 32 bit x 4 bank)
add_mapped_p1=13; //
switch(index)
{
case 0:
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2);
LPC_EMC->DynamicConfig0 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig0 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
case 1:
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2);
LPC_EMC->DynamicConfig1 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig1 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
case 2:
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P2( add_mapped_p2);
LPC_EMC->DynamicConfig2 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig2 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
case 3:
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK;
LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P1(add_mapped_p1);
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK;
LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P2(add_mapped_p2);
LPC_EMC->DynamicConfig3 &= ~EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK;
LPC_EMC->DynamicConfig3 |= EMC_DYNAMIC_CFG_ADD_MAP_P3(add_mapped_p3);
break;
default:
return EMC_FUNC_INVALID_PARAM;
}
return EMC_FUNC_OK;
}The original routine calculated:
add_mapped_p1=17
add_mapped_p2=0
add_mapped_p3=1
but using add_mapped_p1=17 the SDRAM doesn't work fine. I have to force
add_mapped_p1=13
In this way the SDRAM works fine. Why your routine doesn't calcule the right add_mapped_p1 value?
The SDRAM timing I used are the following:
//SDRAM ISSI da 512 Mbit model IS42S32160F_7TLI 16Mx32 (4M x 32 bit x 4 bank)
config.ChipSize = 512; // 512 Mbit total
config.AddrBusWidth = 32; // 32 bit address bus
config.AddrMap = EMC_ADD_MAP_ROW_BANK_COL;
config.CSn = 0;
config.DataWidth = 16;
config.TotalSize = 536870912;
config.CASLatency = 2; // CAS
config.RASLatency = 1; // RAS
config.Active2ActivePeriod = 10; // tRC
config.ActiveBankLatency = 2; // tRRD
config.AutoRefrehPeriod = 10; // tRFC/tRC
config.DataIn2ActiveTime = 5; // tDAL, or tAPW
config.DataOut2ActiveTime = 5; // tAPR
config.WriteRecoveryTime = 2; // tWR, tDPL, tRWL, or tRDL
config.ExitSelfRefreshTime = EMC_NS2CLK(70); // tXSR
config.LoadModeReg2Active = 2; // tMRD
config.PrechargeCmdPeriod = 3; // tRP
config.ReadConfig = 1;
config.RefreshTime = EMC_SDRAM_REFRESH(64);
config.Active2PreChargeTime = 7; // tRAS
config.SeftRefreshExitTime = EMC_NS2CLK(70);
The configuration
add_mapped_p1=13
add_mapped_p2=0
add_mapped_p3=1
correspond to
Your previous suggestion was
I am a little bit confuse.. 
. Can you explain me?
Many thanks
Regards
Hi Nico Aprile,
According to the below statement (Fig 1), the Fig 2 is correct, so I made a mistake before.
Hope this is clear.
Fig 1
Fig 2
Have a great day,
TIC
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Hi jeremyzhou,
many, many thanks!
Your indication is:
Why not the following?:
In other words, what's the bit 12 function
Have a nice day.
Regards
