LPC1788 ADC DMA BURST RTX

[VahidAjalluian]

Hello dear friends,

I am looking for a sample code that fills a buffer automatically with ADC-enabled channels sequentially in LPC1788.

By which I mean if I enable ADC0 to ADC7 and an "unsigned int buffer[8];", The dma would fill the buffer as if the first sample buffer[0] would be the result of adc0, buffer[1] would be the result of adc1, ... and buffer[7] would be the result of adc7.

I have been able to do so with a single channel, but when I enable multiple channels, the sequence is not maintained, by which I mean DMA would fill it in random. For example with "unsigned int buffer[20];" the buffer would fill like ADC0,ADC0,ADC1,ADC0,ADC1,ADC1,ADC0,..... The sample code I have used is the old LPC legacy NXP CMSIS codes which I think were shared in lpcware and no more updated. 

For sure, this capability does exist in STM32 chips, M3 or M4. It would be shameful if such an expensive chip doesn't support this feature.

Sincerely yours

[ZhangJennie]

Hi

For the LPC1788 we don’t have an exact example for it, but we do have the LPCOpen  software available. In there you can find an example of the ADC with DMA mode this could help you reach out if something in your configuration is missing.

If multichannel, The best solution is to use an interrupt, and let the CPU collect the data.

DMA might be used as well. Note only burst requests are supported. The DMS transfer size decides when DMA interrupt is generated. Please check this point.

Both solutions will have the IRQ/DMA request set to the first channel only. The IRA/DMA will then fetch the eight results. Note that the hardware will already have started a new conversion for the first channel, so make sure the previous result are read fast enough.

For more information, see LPC1788 UM, ADC chapter, DMA control.

Hope this helps,

Jun Zhang

[VahidAjalluian]

@ZhangJennie 

Thank you for your reply.

Would you please provide the Lpcopen LPC1788 examples link?

Then you say that It should be able to collect the ADC channels data in sequence order without chaos and mess?

[ZhangJennie]

LPCOpen link:

https://www.nxp.com/design/microcontrollers-developer-resources/lpcopen-libraries-and-examples/lpcop...

Hope this helps,

Jun Zhang

[VahidAjalluian]

Dear @ZhangJennie 

Thank you for your reply.

I investigated the link you provided in advance.

But the problem is it doesn't provide an example with ADC and DMA in multiple ADC channels.

And of course, the datasheet doesn't clarify this case.

Sincerely yours.

[ZhangJennie]

We don't have  example with ADC and DMA in multiple ADC channels for LPC17xx.

There is one for LPC55xx, but LPC55 core and register definition are different with LPC17xx

https://community.nxp.com/t5/LPC-Microcontrollers-Knowledge/ADC-multi-channel-sampling-and-DMA-trans...

[VahidAjalluian]

Dear @ZhangJennie 

LPC55xx series are based on ARM M33, LPC17XX are based on ARM M3. I wonder if the LPC1788 IC layout designer has provided this capability, otherwise, should we change the design.

If the capability exists, why NXP group hesitates to provided it, and if the capability doesn't exist, why such a chip should be this much expensive?

[ZhangJennie]

 LPC17xx can support  DMA in multiple ADC channels without issue. But we don't have demo for LPC17xx. User needs to refer the UM part as I pointed out in my previous reply.

[VahidAjalluian]

@ZhangJennie 

As mentioned before, the settings we had applied to the LPC1788 make it to fill the buffer in mess and chaos. It seems the NXP group is not likely to have software support for previously produced chips unlike other vendors, So finally it seems we should migrate the design from NXP.