LPC1313 system PLL fails to lock on IRC

[lpcware]

Content originally posted in LPCWare by mburton on Wed Mar 06 10:52:18 MST 2013

Hi,

I have a LPC1313 with no external crystal (VDD is 3V) and it is running OK at 12MHz using the IRC but when I try to use the PLL it never locks. I am using lpcopen 1.01 and this is the code used to setup the PLL:

  /* Set system PLL input to IRC */
  Chip_Clock_SetSystemPllSource(SYSCTL_PLLSRC_IRC);

  /* Powerup system PLL */
  Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);

  /* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
  MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
  FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
  FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
  Chip_Clock_SetupSystemPLL(5, 1);

Any

[lpcware]

Content originally posted in LPCWare by lpcadmin on Thu Mar 07 09:47:37 MST 2013
<code>
-__I  uint32_t  RESERVED17[3];
+__I  uint32_t  RESERVED17[4];
</code>

Ouch, that's a bad one - sorry you had to find it, but thanks for identifying it. We'll get this change into the v1.02 release and also check out the full register structure for the CHIP_LPC1343 and CHIP_LPC1347 paths.

[lpcware]

Content originally posted in LPCWare by mburton on Wed Mar 06 15:06:20 MST 2013

Hi,

Well, I found the problem, it's a bug in lpcopen-1.01 that puts PDRUNCFG at the wrong address.

Patch is attached.

Cheers,

Mark

[lpcware]

Content originally posted in LPCWare by mburton on Wed Mar 06 10:53:47 MST 2013
Oops that got posted too soon!

Has anyone got any suggestions as to why the PLL is failing to lock?

Cheers,

Mark