LPC Open Chip_TIMER_Reset() strange behaviour and implementation

[RikkiB]

Hi,

I am using lpcopen_3_02_lpcxpresso_xpresso4337.

When I call Chip_TIMER_Reset(LPC_TIMER2); with no optimisation it takes 480nS but when I call it with -01 optimisation it takes 1.76uS.

This isobviously unexpected. The optimised assembler looks good. 

What it interesting is that most of the time is the while loop in Chip_TIMER_Reset(); 

I cannot see how this is possible.

I suspect the implementation of Chip_TIMER_Reset() is incorrect. It seems overly complicated compared to the CMSIS libraries. Why is TC set to a non zero value in the code below? When it is set to zero the function is much faster.

/* Resets the timer terminal and prescale counts to 0 */
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
{
	uint32_t reg;

	/* Disable timer, set terminal count to non-0 */
	reg = pTMR->TCR;
	pTMR->TCR = 0;
	pTMR->TC = 1;

	/* Reset timer counter */
	pTMR->TCR = TIMER_RESET;

	/* Wait for terminal count to clear */
	while (pTMR->TC != 0) {}

	/* Restore timer state */
	pTMR->TCR = reg;
}

But the CMSIS library code is as follows and seems to do the same thing:

void TIM_ResetCounter(LPC_TIMERn_Type *TIMx)
{
	CHECK_PARAM(PARAM_TIMx(TIMx));
	TIMx->TCR |= TIM_RESET;
	TIMx->TCR &= ~TIM_RESET;
}

Can someone explain>

[xiangjun_rong]

Hi,

Pls refer to section 32.6.2 Timer control register, you have to set the CRST bit, then wait for the bit cleared. so it takes a long time to wait for the bit cleared.

The code is correct.

Chip_TIMER_Reset()

Hope it can help you

BR

XiangJun Rong

[RikkiB]

Hi,

I have read section 32.6.2.

It states:

"When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero."

So it should be reset on the next positive edge of PCLK. Seeing as PCLK is running at 122.88MHz on my board, this should take just over 8nS. Not anything like the values I am seeing:

"with no optimisation it takes 480nS but when I call it with -01 optimisation it takes 1.76uS"

Please can you explain why this is so?

I would also like an explanation of Chip_TIMER_Reset(), in particular why it sets the TC to a not zero value before the reset? There is no explanation for this in the manual?

[xiangjun_rong]

Hi,

I suppose that it is okay to use the following function to reset the CTimer.

void TIM_ResetCounter(LPC_TIMERn_Type *TIMx)
{
	CHECK_PARAM(PARAM_TIMx(TIMx));
	TIMx->TCR |= TIM_RESET;
	TIMx->TCR &= ~TIM_RESET;
}

I have checked the CTimer driver in the recent SDK CTimer driver for the LPC55xx.

static inline void CTIMER_Reset(CTIMER_Type *base)

{

base->TCR |= CTIMER_TCR_CRST_MASK;

base->TCR &= ~CTIMER_TCR_CRST_MASK;

}

Regarding your issue that the time of calling Chip_TIMER_Reset(LPC_TIMER2); is dependent on the

the optimization level, pls check the debug of the function with/without optimization, and check what the problem is.

void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)

Hope it can help you

BR

XiangJun Rong