LCP1549 CAN ISP Bite Rate Timing and Max Cable Length Support

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

LCP1549 CAN ISP Bite Rate Timing and Max Cable Length Support

969 Views
R_B
Contributor I

Hello,

The UM for the 15xx series and section 34.8 C_CAN ISP commands states the on-chip oscillator and the CAN controller are initialized for a CAN bit rate of 100 kbit/s. 

Are the bit timing configurations that are used published somewhere (tq, prop-seg1, prop-seg2, etc)? 

What is the maximum recommended cable length (assuming copper wires) that can be used?

Thanks

 

Labels (1)
0 Kudos
3 Replies

960 Views
frank_m
Senior Contributor III

> What is the maximum recommended cable length (assuming copper wires) that can be used?

That does not depend on the peripheral, but the physical transceiver chip. The MCU only provides the logic-level Rx and Tx pins. The MC33897, PCA82C25x or MCP2551 would be examples of such transceivers.

Since CAN is not a point-to-point bus like RS232, the sheer cable length is less of an criterium, but rather the whole bus configuration and cabling.

> Are the bit timing configurations that are used published somewhere (tq, prop-seg1, prop-seg2, etc)?

I would check the SDKs of you MCU for CAN examples.

0 Kudos

951 Views
R_B
Contributor I

I am looking for the bit timing configurations that are used by the built in CAN bootloader on the part.  I am aware of how to configure the part for CAN communication in my application.

 

0 Kudos

938 Views
diego_charles
NXP TechSupport
NXP TechSupport

Hi @R_B 

You could refer to the LPCopen ROM example periph_ccan_rom , this example uses the boot ROM  API functions for CAN.

The Bit time rate is calculated upon the http://www.bittiming.can-wiki.info/

/* btr values can be obtained from www.bittiming.can-wiki.info (use Bosch C_CAN / D_CAN) */
gCANConfig.btr = 0x0502; /* 500Khz bit rate (%87.5 w 12Mhz base clock ) */

This is applicable if you want to use the boot  ROM API libraries. if you want to use another example ,  the sample point should be  located at 87.5% , between the TSEG1 and TSEG2.

 

I wish this helps!

BR

Diego.

 

0 Kudos