Issue with PD0_SLEEP0_HW_ENA register of LPC4357

[lpcware]

Content originally posted in LPCWare by henna on Sun Jul 05 15:55:17 MST 2015
Hi,

I would like to know how to make m0 as a master which puts the system into deep power down mode.

According to the manual both cores can put the system into any of low power down mode if respective register is set, i.e
PD0_SLEEP0_HW_ENA =0x1 for m4 as a master
PD0_SLEEP0_HW_ENA =0x2 for  m0 as a master.

I tested the PMC demo code of LPCOpen to put the system into deep power down mode when m4 is master which works fine, then I copied the code into m0 project and changed the PD0_SLEEP0_HW_ENA =0x2 register setting to make m0 as a master.

Now the result is if I put the system into a deep power down mode it doesn't works as expected.
1) The current consumption in deep power down mode reduces very low than expected.
2) If I press wake-up button, the system does not come out of the deep power down mode.

I would like know that am I missing something to put the system in low power mode using m0 core as master?

Any help or suggestion will be appreciated.

Thank you.

[lpcware]

Content originally posted in LPCWare by starblue on Thu Jul 09 03:37:39 MST 2015
UM10503, section "11.2.5 Deep power-down": "When the LPC43xx wakes up from Deep power-down mode, the boot loader configures the PLL1 as the clock source running at 96 MHz and attempts to boot in the same way as after a reset or power-up."

Note that on LPC43xx it is always the M4 which boots the system.

[lpcware]

Content originally posted in LPCWare by henna on Wed Jul 08 16:37:57 MST 2015
Hi NXP Support,

I would appreciate if I get some response, as this is really critical for my project.

Thank you.